<s>
The	O
Intel	B-General_Concept
i860	I-General_Concept
(	O
also	O
known	O
as	O
80860	B-General_Concept
)	O
is	O
a	O
RISC	B-Architecture
microprocessor	B-Architecture
design	O
introduced	O
by	O
Intel	O
in	O
1989	O
.	O
</s>
<s>
It	O
is	O
one	O
of	O
Intel	O
's	O
first	O
attempts	O
at	O
an	O
entirely	O
new	O
,	O
high-end	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
since	O
the	O
failed	O
Intel	B-Device
iAPX	I-Device
432	I-Device
from	O
the	O
beginning	O
of	O
the	O
1980s	O
.	O
</s>
<s>
It	O
was	O
released	O
with	O
considerable	O
fanfare	O
,	O
slightly	O
obscuring	O
the	O
earlier	O
Intel	B-General_Concept
i960	I-General_Concept
,	O
which	O
was	O
successful	O
in	O
some	O
niches	O
of	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
The	O
first	O
implementation	O
of	O
the	O
i860	O
architecture	O
is	O
the	O
i860	O
XR	O
microprocessor	B-Architecture
(	O
code-named	O
N10	O
)	O
,	O
which	O
ran	O
at	O
25	O
,	O
33	O
,	O
or	O
40MHz	O
.	O
</s>
<s>
The	O
second-generation	O
i860	O
XP	O
microprocessor	B-Architecture
(	O
code	O
named	O
N11	O
)	O
added	O
4	O
Mbyte	O
pages	O
,	O
larger	O
on-chip	O
caches	O
,	O
second	O
level	O
cache	O
support	O
,	O
faster	O
buses	O
,	O
and	O
hardware	O
support	O
for	O
bus	O
snooping	O
,	O
for	O
cache	O
consistency	O
in	O
multiprocessor	B-Operating_System
systems	O
.	O
</s>
<s>
Both	O
microprocessors	B-Architecture
supported	O
the	O
same	O
instruction	B-General_Concept
set	I-General_Concept
for	O
application	O
programs	O
.	O
</s>
<s>
The	O
i860	O
combined	O
a	O
number	O
of	O
features	O
that	O
were	O
unique	O
at	O
the	O
time	O
,	O
most	O
notably	O
its	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
architecture	O
and	O
powerful	O
support	O
for	O
high-speed	O
floating-point	O
operations	O
.	O
</s>
<s>
The	O
design	O
uses	O
two	O
classes	O
of	O
instructions	O
:	O
"	O
core	O
"	O
instructions	O
which	O
use	O
a	O
32-bit	O
ALU	B-General_Concept
,	O
and	O
"	O
floating-point	O
or	O
graphics	O
"	O
instructions	O
which	O
operate	O
on	O
a	O
floating-point	O
adder	O
,	O
a	O
floating-point	O
multiplier	O
,	O
or	O
a	O
64-bit	O
integer	O
graphics	O
unit	O
.	O
</s>
<s>
The	O
system	O
had	O
separate	O
pipelines	B-General_Concept
for	O
the	O
ALU	B-General_Concept
,	O
floating-point	O
adder	O
,	O
floating-point	O
multiplier	O
,	O
and	O
graphics	O
unit	O
.	O
</s>
<s>
It	O
can	O
fetch	B-General_Concept
and	I-General_Concept
decode	I-General_Concept
one	O
"	O
core	O
"	O
instruction	O
and	O
one	O
"	O
floating-point	O
or	O
graphics	O
"	O
instruction	O
per	O
clock	O
.	O
</s>
<s>
When	O
using	O
dual-operation	O
floating-point	O
instructions	O
(	O
which	O
transfer	O
values	O
between	O
subsequent	O
dual-operation	O
instructions	O
)	O
,	O
it	O
is	O
able	O
to	O
execute	O
up	O
to	O
three	O
operations	O
(	O
one	O
ALU	B-General_Concept
,	O
one	O
floating-point	O
multiply	O
,	O
and	O
one	O
floating-point	O
add-or-subtract	O
)	O
per	O
clock	O
.	O
</s>
<s>
But	O
when	O
executing	O
in	O
dual-instruction	O
mode	O
,	O
the	O
instruction	O
cache	O
is	O
accessed	O
as	O
VLIW	B-General_Concept
instructions	O
consisting	O
of	O
a	O
32-bit	O
"	O
core	O
"	O
instruction	O
paired	O
with	O
a	O
32-bit	O
"	O
floating-point	O
or	O
graphics	O
"	O
instruction	O
,	O
simultaneously	O
fetched	O
together	O
over	O
a	O
64-bit	O
bus	O
.	O
</s>
<s>
Intel	O
referred	O
to	O
the	O
design	O
as	O
the	O
"	O
i860	O
64-Bit	O
Microprocessor	B-Architecture
"	O
.	O
</s>
<s>
Intel	B-General_Concept
i860	I-General_Concept
instructions	O
acted	O
on	O
data	O
sizes	O
from	O
8-bit	O
through	O
128-bit	O
.	O
</s>
<s>
It	O
supported	O
a	O
number	O
of	O
commands	O
for	O
SIMD-like	O
instructions	O
in	O
addition	O
to	O
basic	O
64-bit	O
integer	O
math	O
.	O
</s>
<s>
Experience	O
with	O
the	O
i860	O
influenced	O
the	O
MMX	B-Architecture
functionality	O
later	O
added	O
to	O
Intel	O
's	O
Pentium	B-Device
processors	I-Device
.	O
</s>
<s>
One	O
unusual	O
feature	O
of	O
the	O
i860	O
was	O
that	O
the	O
pipelines	B-General_Concept
into	O
the	O
functional	O
units	O
were	O
program-accessible	O
(	O
VLIW	B-General_Concept
)	O
,	O
requiring	O
the	O
compilers	B-Language
to	O
order	O
instructions	O
carefully	O
in	O
the	O
object	B-Language
code	I-Language
to	O
keep	O
the	O
pipelines	B-General_Concept
filled	O
.	O
</s>
<s>
In	O
traditional	O
architectures	O
these	O
duties	O
were	O
handled	O
at	O
runtime	O
by	O
a	O
scheduler	O
on	O
the	O
CPU	O
itself	O
,	O
but	O
the	O
complexity	O
of	O
these	O
systems	O
limited	O
their	O
application	O
in	O
early	O
RISC	B-Architecture
designs	O
.	O
</s>
<s>
The	O
i860	O
was	O
an	O
attempt	O
to	O
avoid	O
this	O
entirely	O
by	O
moving	O
this	O
duty	O
off-chip	O
into	O
the	O
compiler	B-Language
.	O
</s>
<s>
One	O
problem	O
,	O
perhaps	O
unrecognized	O
at	O
the	O
time	O
,	O
was	O
that	O
runtime	O
code	O
paths	O
are	O
difficult	O
to	O
predict	O
,	O
meaning	O
that	O
it	O
becomes	O
exceedingly	O
difficult	O
to	O
order	O
instructions	O
properly	O
at	O
compile	B-Application
time	I-Application
.	O
</s>
<s>
The	O
entire	O
i860	O
design	O
was	O
based	O
on	O
the	O
compiler	B-Language
efficiently	O
handling	O
this	O
task	O
,	O
which	O
proved	O
almost	O
impossible	O
in	O
practice	O
.	O
</s>
<s>
While	O
theoretically	O
capable	O
of	O
peaking	O
at	O
about	O
60-80	O
MFLOPS	O
for	O
both	O
single	O
precision	O
and	O
double	O
precision	O
for	O
the	O
XP	O
versions	O
,	O
manually	O
written	O
assembler	O
code	O
managed	O
to	O
get	O
only	O
about	O
up	O
to	O
40	O
MFLOPS	O
,	O
and	O
most	O
compilers	B-Language
had	O
difficulty	O
getting	O
even	O
10	O
MFLOPs	O
.	O
</s>
<s>
The	O
later	O
Itanium	B-General_Concept
architecture	O
,	O
also	O
a	O
VLIW	B-General_Concept
design	O
,	O
suffered	O
again	O
from	O
the	O
problem	O
of	O
compilers	B-Language
incapable	O
of	O
delivering	O
sufficiently	O
optimized	O
code	O
.	O
</s>
<s>
Another	O
serious	O
problem	O
was	O
the	O
lack	O
of	O
any	O
solution	O
to	O
handle	O
context	B-Operating_System
switching	I-Operating_System
quickly	O
.	O
</s>
<s>
The	O
i860	O
had	O
several	O
pipelines	B-General_Concept
(	O
for	O
the	O
ALU	B-General_Concept
and	O
FPU	O
parts	O
)	O
and	O
an	O
interrupt	O
could	O
spill	O
them	O
and	O
require	O
them	O
all	O
to	O
be	O
re-loaded	O
.	O
</s>
<s>
As	O
the	O
compilers	B-Language
improved	O
,	O
the	O
general	O
performance	O
of	O
the	O
i860	O
did	O
likewise	O
,	O
but	O
by	O
then	O
most	O
other	O
RISC	B-Architecture
designs	O
had	O
already	O
passed	O
the	O
i860	O
in	O
performance	O
.	O
</s>
<s>
In	O
the	O
late	O
1990s	O
,	O
Intel	O
replaced	O
their	O
entire	O
RISC	B-Architecture
line	O
with	O
ARM-based	O
designs	O
,	O
known	O
as	O
the	O
XScale	B-Application
.	O
</s>
<s>
Confusingly	O
,	O
the	O
860	O
number	O
has	O
since	O
been	O
re-used	O
for	O
a	O
motherboard	O
control	O
chipset	O
for	O
Intel	B-Device
Xeon	I-Device
(	O
high-end	O
Pentium	B-Device
)	O
systems	O
and	O
a	O
model	O
of	O
the	O
Core	O
i7	O
.	O
</s>
<s>
At	O
first	O
,	O
the	O
i860	O
was	O
only	O
used	O
in	O
a	O
small	O
number	O
of	O
supercomputers	B-Architecture
such	O
as	O
the	O
Intel	O
iPSC/860	O
.	O
</s>
<s>
Intel	O
later	O
marketed	O
the	O
i860	O
as	O
a	O
workstation	B-Device
microprocessor	B-Architecture
for	O
a	O
time	O
,	O
where	O
it	O
competed	O
with	O
microprocessors	B-Architecture
based	O
on	O
the	O
MIPS	B-Device
and	O
SPARC	B-Architecture
architectures	O
,	O
among	O
others	O
.	O
</s>
<s>
The	O
Oki	O
Electric	O
OKI	O
Station	O
7300/30	O
and	O
Stardent	O
Vistra	O
800	O
Unix	B-Device
workstations	I-Device
were	O
based	O
on	O
a	O
40MHz	O
i860	O
XR	O
running	O
UNIX	O
System	O
V/i860	O
.	O
</s>
<s>
The	O
Hauppauge	O
4860	O
and	O
Olivetti	O
CP486	O
featured	O
an	O
Intel	B-General_Concept
80486	I-General_Concept
and	O
i860	O
on	O
the	O
same	O
motherboard	O
.	O
</s>
<s>
Microsoft	O
initially	O
developed	O
what	O
was	O
to	O
become	O
Windows	B-Device
NT	I-Device
on	O
internally	O
designed	O
i860XR-based	O
workstations	B-Device
(	O
codenamed	O
Dazzle	O
)	O
,	O
only	O
porting	O
NT	O
to	O
the	O
MIPS	B-Device
(	O
Microsoft	B-Device
Jazz	I-Device
)	O
,	O
Intel	B-General_Concept
80386	I-General_Concept
and	O
other	O
processors	O
later	O
.	O
</s>
<s>
The	O
i860	O
did	O
see	O
some	O
use	O
in	O
the	O
workstation	B-Device
world	O
as	O
a	O
graphics	O
accelerator	O
.	O
</s>
<s>
It	O
was	O
used	O
,	O
for	O
instance	O
,	O
in	O
the	O
NeXTdimension	B-Device
,	O
where	O
it	O
ran	O
a	O
cut-down	O
version	O
of	O
the	O
Mach	B-Operating_System
kernel	I-Operating_System
running	O
a	O
complete	O
PostScript	B-Language
stack	O
.	O
</s>
<s>
However	O
,	O
the	O
PostScript	B-Language
part	O
of	O
the	O
project	O
was	O
never	O
finished	O
so	O
it	O
ended	O
up	O
just	O
moving	O
color	O
pixels	O
around	O
.	O
</s>
<s>
In	O
this	O
role	O
,	O
the	O
i860	O
design	O
worked	O
considerably	O
better	O
,	O
as	O
the	O
core	O
program	O
could	O
be	O
loaded	O
into	O
the	O
cache	O
and	O
made	O
entirely	O
"	O
predictable	O
"	O
,	O
allowing	O
the	O
compilers	B-Language
to	O
get	O
the	O
ordering	O
right	O
.	O
</s>
<s>
Pixar	O
produced	O
a	O
custom	O
version	O
of	O
RenderMan	B-Application
to	O
run	O
on	O
the	O
card	O
that	O
ran	O
approximately	O
four	O
times	O
faster	O
than	O
the	O
386	B-General_Concept
host	O
.	O
</s>
<s>
This	O
sort	O
of	O
use	O
slowly	O
disappeared	O
as	O
well	O
,	O
as	O
more	O
general-purpose	O
CPUs	O
started	O
to	O
match	O
the	O
i860	O
's	O
performance	O
,	O
and	O
as	O
Intel	O
turned	O
its	O
focus	O
to	O
Pentium	B-Device
processors	I-Device
for	O
general-purpose	O
computing	O
.	O
</s>
<s>
Mercury	B-Application
Computer	I-Application
Systems	I-Application
used	O
the	O
i860	O
in	O
their	O
multicomputer	B-Operating_System
.	O
</s>
<s>
From	O
2	O
to	O
360	O
compute	O
nodes	O
would	O
reside	O
in	O
a	O
circuit	B-Protocol
switched	I-Protocol
fat	B-Protocol
tree	I-Protocol
network	O
,	O
with	O
each	O
node	O
having	O
local	O
memory	O
that	O
could	O
be	O
mapped	O
by	O
any	O
other	O
node	O
.	O
</s>
<s>
Each	O
node	O
in	O
this	O
heterogeneous	O
system	O
could	O
be	O
an	O
i860	O
,	O
a	O
PowerPC	B-Architecture
,	O
or	O
a	O
group	O
of	O
three	O
SHARC	B-General_Concept
DSPs	O
.	O
</s>
<s>
The	O
hardware	O
packed	O
up	O
to	O
360	O
compute	O
nodes	O
in	O
9U	O
of	O
rack	B-Application
space	O
,	O
making	O
it	O
suitable	O
for	O
mobile	O
applications	O
such	O
as	O
airborne	O
radar	O
processing	O
.	O
</s>
<s>
During	O
the	O
early	O
1990s	O
,	O
Stratus	B-General_Concept
Technologies	I-General_Concept
built	O
i860-based	O
servers	O
,	O
the	O
XA/R	O
series	O
,	O
running	O
their	O
proprietary	O
VOS	B-General_Concept
operating	O
system	O
.	O
</s>
<s>
Both	O
the	O
Alliant	O
and	O
Mercury	O
compute	O
systems	O
were	O
in	O
heavy	O
use	O
at	O
NASA/JPL	O
for	O
the	O
SIR-C	B-Algorithm
missions	O
.	O
</s>
<s>
The	O
U.S.	O
military	O
used	O
the	O
i860	O
for	O
numerous	O
aerospace	O
and	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
applications	O
as	O
a	O
coprocessor	O
,	O
where	O
it	O
saw	O
use	O
up	O
until	O
the	O
late	O
1990s	O
.	O
</s>
