<s>
The	O
Intel	B-General_Concept
i750	I-General_Concept
is	O
a	O
two-chip	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
composed	O
of	O
the	O
82750PB	O
pixel	O
processor	O
and	O
82750DB	O
display	O
processor	O
.	O
</s>
<s>
The	O
i750	B-General_Concept
chip	O
was	O
used	O
in	O
video	O
capture/compression	O
cards	O
such	O
as	O
the	O
Intel	O
Smart	O
Video	O
Recorder	O
and	O
Creative	O
Labs	O
Video	O
Blaster	O
RT300	O
.	O
</s>
<s>
Although	O
Intel	O
had	O
made	O
earlier	O
chips	O
targeting	O
graphics	O
(	O
e.g.	O
,	O
82786	O
graphics	B-Architecture
coprocessor	I-Architecture
)	O
,	O
this	O
could	O
be	O
considered	O
as	O
Intel	O
's	O
first	O
attempt	O
to	O
break	O
into	O
the	O
video	B-Device
controller	I-Device
marketplace	O
.	O
</s>
<s>
The	O
Indeo	B-Algorithm
video	I-Algorithm
compressor	O
was	O
originally	O
built	O
to	O
work	O
with	O
the	O
i750	B-General_Concept
,	O
but	O
was	O
later	O
ported	O
to	O
other	O
systems	O
as	O
well	O
.	O
</s>
<s>
It	O
contains	O
57	O
instruction	O
set	O
,	O
eight	O
entries	O
64	O
bit	O
vector	O
registers	O
(	O
same	O
MM0	O
~	O
MM7	O
register	O
naming	O
as	O
used	O
on	O
the	O
x86	O
,	O
the	O
only	O
difference	O
being	O
that	O
i750	B-General_Concept
has	O
dedicated	O
registers	O
while	O
the	O
x86	O
MMX	O
CPU	O
does	O
not	O
.	O
</s>
<s>
However	O
,	O
the	O
i750	B-General_Concept
lacks	O
general	O
purpose	O
integer	O
registers	O
unlike	O
its	O
x86	O
counterpart	O
)	O
,	O
a	O
64-bit	O
ALU	O
,	O
a	O
512×	O
48-bit	O
instruction	O
RAM	O
,	O
a	O
512×	O
16-bit	O
data	O
RAM	O
,	O
two	O
internal	O
16-bit	O
buses	O
,	O
a	O
wide	O
instruction	O
word	O
processor	O
,	O
a	O
variable	O
length	O
sequence	O
decoder	O
,	O
a	O
pixel	O
interpolator	O
and	O
an	O
interface	O
supporting	O
a	O
4	O
GB	O
linear	O
address	O
space	O
.	O
</s>
<s>
Intel	O
's	O
low-cost	O
i750	B-General_Concept
processor	O
,	O
82750PD	O
,	O
and	O
ATI	O
's	O
68890	O
video	O
capture	O
Chip	O
for	O
video-only	O
boards	O
.	O
</s>
