<s>
Intel	B-General_Concept
Xe	I-General_Concept
(	O
stylized	O
as	O
Xe	O
and	O
pronounced	O
as	O
two	O
separate	O
letters	O
,	O
abbreviation	O
for	O
"	O
eXascale	B-General_Concept
for	O
everyone	O
"	O
)	O
,	O
earlier	O
known	O
unofficially	O
as	O
Gen12	O
,	O
is	O
a	O
GPU	B-Architecture
architecture	B-General_Concept
developed	O
by	O
Intel	O
.	O
</s>
<s>
Intel	B-General_Concept
Xe	I-General_Concept
includes	O
a	O
new	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
The	O
Xe	O
GPU	B-Architecture
family	O
consists	O
of	O
a	O
series	O
of	O
microarchitectures	B-General_Concept
,	O
ranging	O
from	O
integrated/low	O
power	O
(	O
Xe-LP	O
)	O
,	O
to	O
enthusiast/high	O
performance	O
gaming	O
(	O
Xe-HPG	O
)	O
,	O
datacenter/high	O
performance	O
(	O
Xe-HP	O
)	O
and	O
high	B-Architecture
performance	I-Architecture
computing	I-Architecture
(	O
Xe-HPC	O
)	O
.	O
</s>
<s>
Intel	O
's	O
first	O
attempt	O
at	O
a	O
dedicated	O
graphics	B-Device
card	I-Device
was	O
the	O
Intel740	B-General_Concept
,	O
released	O
in	O
February	O
1998	O
.	O
</s>
<s>
The	O
Intel740	B-General_Concept
was	O
considered	O
unsuccessful	O
due	O
to	O
its	O
performance	O
which	O
was	O
lower	O
than	O
market	O
expectations	O
,	O
causing	O
Intel	O
to	O
cease	O
development	O
on	O
future	O
discrete	B-Device
graphics	I-Device
products	O
.	O
</s>
<s>
However	O
,	O
its	O
technology	O
lived	O
on	O
in	O
the	O
Intel	B-Device
Extreme	I-Device
Graphics	I-Device
lineup	O
.	O
</s>
<s>
Intel	O
made	O
another	O
attempt	O
with	O
the	O
Larrabee	B-Architecture
architecture	B-General_Concept
before	O
canceling	O
it	O
in	O
2009	O
;	O
this	O
time	O
,	O
the	O
technology	O
developed	O
was	O
used	O
in	O
the	O
Xeon	B-General_Concept
Phi	I-General_Concept
,	O
which	O
was	O
discontinued	O
in	O
2020	O
.	O
</s>
<s>
In	O
April	O
2018	O
,	O
it	O
was	O
reported	O
that	O
Intel	O
was	O
assembling	O
a	O
team	O
to	O
develop	O
discrete	B-Device
graphics	I-Device
processing	O
units	O
,	O
targeting	O
both	O
datacenters	B-Operating_System
,	O
as	O
well	O
as	O
the	O
PC	O
gaming	O
market	O
,	O
and	O
therefore	O
competitive	O
with	O
products	O
from	O
both	O
Nvidia	B-Application
and	O
AMD	B-Device
.	O
</s>
<s>
Rumors	O
supporting	O
the	O
claim	O
included	O
that	O
the	O
company	O
had	O
vacancies	O
for	O
over	O
100	O
graphics-related	O
jobs	O
,	O
and	O
had	O
taken	O
on	O
former	O
Radeon	B-Device
Technologies	I-Device
Group	I-Device
(	O
AMD	B-Device
)	O
leader	O
Raja	O
Koduri	O
in	O
late	O
2017	O
–	O
the	O
new	O
product	O
was	O
reported	O
to	O
be	O
codenamed	O
"	O
Arctic	O
Sound	O
"	O
.	O
</s>
<s>
The	O
project	O
was	O
reported	O
to	O
have	O
initially	O
been	O
targeting	O
video	O
streaming	O
chips	O
for	O
data	B-Operating_System
centers	I-Operating_System
,	O
but	O
had	O
its	O
scope	O
expanded	O
to	O
include	O
desktop	O
GPUs	B-Architecture
.	O
</s>
<s>
In	O
June	O
2018	O
,	O
Intel	O
confirmed	O
it	O
planned	O
to	O
launch	O
a	O
discrete	B-Device
GPU	I-Device
in	O
2020	O
.	O
</s>
<s>
The	O
first	O
functional	O
discrete	O
"	O
Xe	O
"	O
GPU	B-Architecture
,	O
codenamed	O
"	O
DG1	B-General_Concept
"	O
,	O
was	O
reported	O
as	O
having	O
begun	O
testing	O
in	O
October	O
2019	O
.	O
</s>
<s>
According	O
to	O
a	O
report	O
by	O
Hexus	O
in	O
late	O
2019	O
,	O
a	O
discrete	B-Device
GPU	I-Device
would	O
launch	O
in	O
mid	O
2020	O
;	O
combined	O
GPU/CPU	O
(	O
GPGPU	B-Architecture
)	O
products	O
were	O
also	O
expected	O
,	O
for	O
data	B-Operating_System
center	I-Operating_System
and	O
autonomous	O
driving	O
applications	O
.	O
</s>
<s>
The	O
product	O
is	O
expected	O
to	O
be	O
initially	O
built	O
on	O
a	O
10	B-Algorithm
nm	I-Algorithm
node	O
(	O
with	O
7	B-Algorithm
nm	I-Algorithm
products	O
in	O
2021	O
)	O
and	O
use	O
Intel	O
's	O
Foveros	B-Architecture
die	O
stacking	O
packaging	O
technology	O
(	O
see	O
3D	B-Architecture
die	I-Architecture
stacking	I-Architecture
)	O
.	O
</s>
<s>
Intel	B-General_Concept
Xe	I-General_Concept
expands	O
upon	O
the	O
microarchitectural	B-General_Concept
overhaul	O
introduced	O
in	O
Gen	B-Application
11	I-Application
with	O
a	O
full	O
refactor	O
of	O
the	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
The	O
Xe	O
GPU	B-Architecture
family	O
consists	O
of	O
Xe-LP	O
,	O
Xe-HP	O
,	O
Xe-HPC	O
,	O
and	O
Xe-HPG	O
sub-architectures	O
.	O
</s>
<s>
Unlike	O
previous	O
Intel	B-Device
graphics	I-Device
processing	I-Device
units	I-Device
which	O
used	O
the	O
Execution	O
Unit	O
(	O
EU	O
)	O
as	O
a	O
compute	O
unit	O
,	O
Xe-HPG	O
and	O
Xe-HPC	O
use	O
the	O
Xe-core	O
.	O
</s>
<s>
An	O
Xe-core	O
contains	O
vector	O
and	O
matrix	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
,	O
which	O
are	O
referred	O
to	O
as	O
vector	O
and	O
matrix	O
engines	O
.	O
</s>
<s>
Xe-LP	O
is	O
the	O
low	O
power	O
variant	O
of	O
the	O
Xe	O
architecture	B-General_Concept
.	O
</s>
<s>
Xe-LP	O
is	O
present	O
as	O
integrated	O
graphics	O
for	O
11th-generation	O
Intel	O
Core	O
and	O
the	O
Iris	B-General_Concept
Xe	I-General_Concept
MAX	O
mobile	O
dedicated	O
GPU	B-Architecture
(	O
codenamed	O
DG1	B-General_Concept
)	O
,	O
as	O
well	O
as	O
in	O
the	O
H3C	O
XG310	O
Intel	O
Server	O
GPU	B-Architecture
(	O
codenamed	O
SG1	O
)	O
.	O
</s>
<s>
Compared	O
to	O
its	O
predecessor	O
,	O
Xe-LP	O
includes	O
new	O
features	O
such	O
as	O
Sampler	O
Feedback	O
,	O
Dual	O
Queue	O
Support	O
,	O
DirectX12	O
View	O
Instancing	O
Tier2	O
,	O
and	O
AV1	B-Application
8-bit	O
and	O
10-bit	O
fixed-function	O
hardware	O
decoding	O
.	O
</s>
<s>
Xe-HP	O
is	O
the	O
datacenter/high	O
performance	O
variant	O
of	O
Xe	O
,	O
optimized	O
for	O
FP64	O
performance	O
and	O
multi-tile	O
scalability	O
.	O
</s>
<s>
Xe-HPC	O
is	O
the	O
high	B-Architecture
performance	I-Architecture
computing	I-Architecture
variant	O
of	O
the	O
Xe	O
architecture	B-General_Concept
.	O
</s>
<s>
An	O
Xe-HPC	O
Xe-core	O
contains	O
8	O
vector	O
and	O
8	O
matrix	O
engines	O
,	O
alongside	O
a	O
large	O
512	O
KB	O
L1	O
cache	O
.	O
</s>
<s>
Xe-HPG	O
is	O
the	O
enthusiast	O
or	O
high	O
performance	O
graphics	O
variant	O
of	O
the	O
Xe	O
architecture	B-General_Concept
.	O
</s>
<s>
The	O
microarchitecture	B-General_Concept
is	O
based	O
on	O
Xe-LP	O
with	O
improvements	O
from	O
Xe-HP	O
and	O
Xe-HPC	O
.	O
</s>
<s>
The	O
microarchitecture	B-General_Concept
is	O
focused	O
on	O
graphics	O
performance	O
and	O
supports	O
hardware-accelerated	B-Algorithm
ray	I-Algorithm
tracing	I-Algorithm
,	O
DisplayPort	B-Protocol
2.0	O
,	O
XeSS	O
or	O
supersampling	O
based	O
on	O
neural	O
networks	O
(	O
similar	O
to	O
Nvidia	B-Device
DLSS	I-Device
)	O
,	O
and	O
DirectX	O
12	O
Ultimate	O
.	O
</s>
<s>
Intel	O
confirmed	O
ASTC	O
support	O
has	O
been	O
removed	O
from	O
hardware	O
starting	O
with	O
Alchemist	O
and	O
future	O
Intel	B-Device
Arc	I-Device
GPU	B-Architecture
microarchitectures	B-General_Concept
will	O
also	O
not	O
support	O
it	O
.	O
</s>
<s>
An	O
Xe-HPG	O
render	O
slice	O
will	O
consist	O
of	O
four	O
Xe-cores	O
,	O
ray	B-Algorithm
tracing	I-Algorithm
hardware	I-Algorithm
,	O
and	O
other	O
components	O
.	O
</s>
<s>
A	O
successor	O
to	O
Xe	O
was	O
revealed	O
during	O
Intel	O
Architecture	B-General_Concept
Day	O
2021	O
,	O
under	O
the	O
name	O
of	O
Xe	O
2	O
,	O
codenamed	O
Battlemage	O
.	O
</s>
<s>
In	O
an	O
exclusive	O
Interview	O
with	O
HardwareLuxx	O
Tom	O
Peterson	O
confirmed	O
that	O
Xe2	O
will	O
be	O
segmented	O
into	O
"	O
Xe2-LPG	O
"	O
(	O
Low	O
Power	O
Graphics	O
)	O
for	O
integrated	O
GPUs	B-Architecture
and	O
"	O
Xe2-HPG	O
"	O
(	O
High	O
Performane	O
Graphics	O
)	O
for	O
discrete	B-Device
GPUs	I-Device
.	O
</s>
<s>
Intel	B-General_Concept
Xe	I-General_Concept
3	O
is	O
the	O
upcoming	O
successor	O
to	O
the	O
Intel	B-General_Concept
Xe	I-General_Concept
2	O
microarchitecture	B-General_Concept
codenamed	O
Celestial	O
and	O
is	O
scheduled	O
for	O
a	O
2024	O
release	O
as	O
per	O
Intel	O
's	O
GPU	B-Architecture
roadmap	O
.	O
</s>
<s>
Intel	B-General_Concept
Xe	I-General_Concept
4	O
is	O
the	O
upcoming	O
successor	O
to	O
the	O
Intel	B-General_Concept
Xe	I-General_Concept
3	O
microarchitecture	B-General_Concept
codenamed	O
Druid	O
.	O
</s>
<s>
Newer	O
Intel	O
processors	O
use	O
the	O
Xe-LP	O
microarchitecture	B-General_Concept
.	O
</s>
<s>
These	O
include	O
11th	O
generation	O
Intel	O
Core	O
processors	O
(	O
codenamed	O
"	O
Tiger	B-Device
Lake	I-Device
"	O
and	O
"	O
Rocket	B-Device
Lake	I-Device
"	O
)	O
,	O
12th	O
generation	O
Intel	O
Core	O
processors	O
(	O
codenamed	O
"	O
Alder	B-Device
Lake	I-Device
"	O
)	O
,	O
and	O
13th	O
generation	O
Intel	O
Core	O
processors	O
(	O
codenamed	O
"	O
Raptor	B-Device
Lake	I-Device
"	O
)	O
.	O
</s>
<s>
In	O
August	O
2020	O
,	O
Intel	O
was	O
reported	O
to	O
be	O
shipping	O
Xe	O
DG1	B-General_Concept
GPUs	B-Architecture
for	O
a	O
possible	O
late	O
2020	O
release	O
,	O
while	O
also	O
commenting	O
on	O
a	O
DG2	O
GPU	B-Architecture
aimed	O
at	O
the	O
enthusiast	O
market	O
(	O
later	O
found	O
out	O
to	O
be	O
the	O
first	O
generation	O
of	O
Intel	B-Device
Arc	I-Device
nicknamed	O
"	O
Alchemist	O
"	O
)	O
.	O
</s>
<s>
The	O
DG1	B-General_Concept
is	O
also	O
sold	O
as	O
the	O
Iris	B-General_Concept
Xe	I-General_Concept
MAX	O
and	O
as	O
Iris	B-General_Concept
Xe	I-General_Concept
Graphics	O
(	O
stylized	O
as	O
iRIS	B-General_Concept
Xe	I-General_Concept
)	O
in	O
laptops	O
,	O
while	O
cards	O
for	O
developers	O
are	O
sold	O
as	O
the	O
DG1	B-General_Concept
SDV	O
.	O
</s>
<s>
The	O
Xe	O
MAX	O
is	O
an	O
entry-level	O
GPU	B-Architecture
that	O
was	O
first	O
released	O
on	O
November	O
1	O
,	O
2020	O
,	O
in	O
China	O
and	O
is	O
similar	O
in	O
most	O
aspects	O
to	O
the	O
integrated	O
GPU	B-Architecture
found	O
in	O
Tiger	B-Device
Lake	I-Device
processors	O
,	O
the	O
only	O
differences	O
being	O
a	O
higher	O
clock	O
speed	O
,	O
slightly	O
higher	O
performance	O
and	O
dedicated	O
memory	O
and	O
a	O
dedicated	O
TDP	O
requirement	O
.	O
</s>
<s>
It	O
competes	O
with	O
Nvidia	B-Application
's	O
laptop-level	O
GeForce	B-Application
MX	O
series	O
GPUs	B-Architecture
.	O
</s>
<s>
The	O
Xe	O
MAX	O
does	O
not	O
replace	O
the	O
system	O
's	O
integrated	O
GPU	B-Architecture
;	O
instead	O
it	O
was	O
designed	O
to	O
work	O
alongside	O
it	O
,	O
so	O
tasks	O
are	O
split	O
between	O
the	O
integrated	O
and	O
discrete	B-Device
GPUs	I-Device
.	O
</s>
<s>
Intel	B-General_Concept
Xe	I-General_Concept
MAX	O
GPUs	B-Architecture
can	O
only	O
be	O
found	O
on	O
systems	O
with	O
Tiger	B-Device
Lake	I-Device
processors	O
.	O
</s>
<s>
Intel	O
officially	O
announced	O
Intel	B-General_Concept
Iris	I-General_Concept
Xe	I-General_Concept
Graphics	O
desktop	O
cards	O
for	O
OEMs	O
and	O
system	O
integrators	O
on	O
January	O
26	O
,	O
2021	O
.	O
</s>
<s>
It	O
is	O
aimed	O
at	O
mainstream	O
desktop	O
and	O
business	O
PCs	O
as	O
an	O
improvement	O
over	O
other	O
graphics	O
options	O
in	O
AV1	B-Application
video	O
decoding	O
,	O
HDR	O
(	O
high	O
dynamic	O
range	O
)	O
video	O
support	O
and	O
deep	O
learning	O
inference	O
,	O
and	O
is	O
not	O
as	O
powerful	O
as	O
its	O
laptop	O
counterpart	O
,	O
with	O
only	O
80	O
enabled	O
EUs	O
.	O
</s>
<s>
The	O
first	O
cards	O
are	O
made	O
by	O
Asus	O
,	O
have	O
DisplayPort	B-Protocol
1.4	O
,	O
HDMI	B-Protocol
2.0	O
,	O
Dual	O
Link	O
DL-DVI-D	O
outputs	O
and	O
are	O
passively	O
cooled	O
.	O
</s>
<s>
Intel	B-Device
Arc	I-Device
is	O
a	O
high-performance	O
discrete	B-Device
graphics	I-Device
line	O
optimized	O
for	O
gaming	O
.	O
</s>
<s>
This	O
will	O
compete	O
directly	O
with	O
the	O
Radeon	B-Device
and	O
GeForce	B-Application
lines	O
of	O
graphics	B-Architecture
processing	I-Architecture
units	I-Architecture
.	O
</s>
<s>
The	O
first	O
generation	O
(	O
codenamed	O
"	O
Alchemist	O
"	O
)	O
,	O
was	O
developed	O
under	O
the	O
"	O
DG2	O
"	O
name	O
and	O
is	O
based	O
on	O
the	O
Xe-HPG	O
architecture	B-General_Concept
.	O
</s>
<s>
Intel	O
officially	O
announced	O
their	O
Xe	O
general	O
HPC/AI	O
GPU	B-Architecture
codenamed	O
Ponte	O
Vecchio	O
on	O
November	O
17	O
,	O
2019	O
.	O
</s>
<s>
It	O
was	O
revealed	O
to	O
use	O
the	O
Xe-HPC	O
variant	O
of	O
the	O
architecture	B-General_Concept
and	O
Intel	O
's	O
'	O
Embedded	O
Multi-Die	O
Interconnect	O
Bridge	O
 '	O
(	O
EMIB	O
)	O
and	O
Foveros	B-Architecture
die	O
stacking	O
packaging	O
on	O
a	O
Intel	B-Algorithm
4	I-Algorithm
node	O
(	O
previously	O
referred	O
to	O
as	O
7nm	B-Algorithm
)	O
.	O
</s>
<s>
Intel	O
later	O
confirmed	O
at	O
Architecture	B-General_Concept
Day	O
2021	O
that	O
Ponte	O
Vecchio	O
would	O
use	O
Compute	O
Tiles	O
manufactured	O
on	O
TSMC	O
N5	O
,	O
Base	O
Tiles	O
and	O
Rambo	O
Cache	O
Tiles	O
manufactured	O
using	O
Intel	B-Algorithm
7	I-Algorithm
(	O
previously	O
referred	O
to	O
as	O
10nm	B-Algorithm
Enhanced	O
SuperFin	O
)	O
and	O
Xe	O
Link	O
Tiles	O
manufactured	O
on	O
the	O
TSMC	O
N7	O
process	O
.	O
</s>
<s>
The	O
new	O
GPU	B-Architecture
is	O
expected	O
to	O
be	O
used	O
in	O
Argonne	O
National	O
Laboratory	O
's	O
new	O
exascale	B-General_Concept
supercomputer	I-General_Concept
,	O
Aurora	B-Device
,	O
with	O
compute	O
nodes	O
comprising	O
two	O
next	O
generation	O
Intel	B-Device
Xeon	I-Device
(	O
codenamed	O
"	O
Sapphire	B-Device
Rapids	I-Device
"	O
)	O
CPUs	O
,	O
and	O
six	O
Ponte	O
Vecchio	O
GPUs	B-Architecture
.	O
</s>
