<s>
Intel	B-Device
X99	I-Device
,	O
codenamed	B-Architecture
"	O
Wellsburg	O
"	O
,	O
is	O
a	O
Platform	B-Device
Controller	I-Device
Hub	I-Device
(	O
PCH	O
)	O
designed	O
and	O
manufactured	O
by	O
Intel	O
,	O
targeted	O
at	O
the	O
high-end	B-Device
desktop	I-Device
(	O
HEDT	O
)	O
and	O
enthusiast	O
segments	O
of	O
the	O
Intel	O
product	O
lineup	O
.	O
</s>
<s>
The	O
X99	B-Device
chipset	O
supports	O
both	O
Intel	O
Core	O
i7	O
Extreme	O
and	O
Intel	B-Device
Xeon	I-Device
E5-16xxv3	O
and	O
E5-26xxv3	O
processors	B-General_Concept
,	O
which	O
belong	O
to	O
the	O
Haswell-E	O
and	O
Haswell-EP	O
variants	O
of	O
the	O
Haswell	B-Device
microarchitecture	I-Device
,	O
respectively	O
.	O
</s>
<s>
All	O
supported	O
processors	B-General_Concept
use	O
the	O
LGA	O
2011-v3	O
socket	B-General_Concept
.	O
</s>
<s>
The	O
X99	B-Device
chipset	O
was	O
released	O
in	O
late	O
August	O
2014	O
,	O
while	O
the	O
supported	O
processors	B-General_Concept
were	O
released	O
in	O
late	O
August	O
2014	O
(	O
Haswell-E	O
)	O
and	O
early	O
September	O
2014	O
(	O
Haswell-EP	O
)	O
.	O
</s>
<s>
In	O
May	O
2016	O
,	O
X99	B-Device
's	O
processor	O
support	O
was	O
extended	O
to	O
the	O
Broadwell	B-General_Concept
variants	O
of	O
the	O
Intel	O
Corei7	O
Extreme	O
and	O
Intel	B-Device
Xeon	I-Device
E5-16xxv4	O
and	O
E5-26xxv4	O
processors	B-General_Concept
,	O
which	O
belong	O
to	O
the	O
Broadwell-E	B-General_Concept
and	O
Broadwell-EP	O
variants	O
of	O
the	O
Broadwell	B-General_Concept
microarchitecture	B-General_Concept
,	O
respectively	O
.	O
</s>
<s>
The	O
X99	B-Device
chipset	O
uses	O
a	O
Direct	B-Architecture
Media	I-Architecture
Interface	I-Architecture
(	O
DMI	O
)	O
2.0	O
×4	O
link	O
for	O
the	O
connection	O
between	O
the	O
processor	O
and	O
itself	O
;	O
that	O
way	O
,	O
a	O
total	O
bandwidth	O
of	O
20Gbit/s	O
is	O
available	O
to	O
all	O
connectivity	O
options	O
provided	O
by	O
the	O
chipset	O
.	O
</s>
<s>
Up	O
to	O
eight	O
PCI	O
Express	O
2.0	O
lanes	O
are	O
provided	O
by	O
the	O
X99	B-Device
chipset	O
,	O
with	O
speeds	O
of	O
up	O
to	O
5Gbit/s	O
per	O
lane	O
and	O
a	O
possibility	O
to	O
configure	O
these	O
lanes	O
into	O
×1	O
,	O
×2	O
and	O
×4	O
links	O
.	O
</s>
<s>
Additionally	O
,	O
the	O
X99	B-Device
chipset	O
supports	O
a	O
configurable	O
layout	O
of	O
the	O
PCI	O
Express	O
3.0	O
lanes	O
provided	O
by	O
the	O
processor	O
,	O
which	O
may	O
be	O
bifurcated	O
into	O
up	O
to	O
two	O
×16	O
links	O
and	O
one	O
×8	O
link	O
,	O
or	O
into	O
up	O
to	O
five	O
×8	O
links	O
(	O
the	O
total	O
number	O
of	O
available	O
PCI	O
Express3.0	O
lanes	O
depends	O
on	O
the	O
used	O
processor	O
)	O
.	O
</s>
<s>
Two	O
Serial	O
ATA	O
(	O
SATA	O
)	O
3.0	O
controllers	O
are	O
integrated	O
into	O
the	O
X99	B-Device
chipset	O
,	O
providing	O
a	O
total	O
of	O
up	O
to	O
ten	O
ports	O
for	O
storage	O
devices	O
and	O
supporting	O
speeds	O
of	O
up	O
to	O
6Gbit/s	O
per	O
port	O
,	O
with	O
hardware	O
support	O
for	O
the	O
Advanced	O
Host	O
Controller	O
Interface	O
(	O
AHCI	O
)	O
logical	O
interface	O
.	O
</s>
<s>
Six	O
SATA	O
ports	O
provided	O
by	O
the	O
first	O
controller	O
may	O
be	O
configured	O
for	O
Rapid	B-Application
Storage	I-Application
Technology	I-Application
(	O
RST	O
)	O
13.1	O
,	O
which	O
supports	O
RAID0	O
,	O
1	O
,	O
5	O
and	O
10	O
levels	O
;	O
additionally	O
,	O
Smart	B-Device
Response	I-Device
Technology	I-Device
(	O
SRT	O
)	O
disk	O
caching	O
allows	O
the	O
creation	O
of	O
hybrid	O
volumes	O
.	O
</s>
<s>
SATA	B-Architecture
Express	I-Architecture
and	O
M.2	B-Protocol
are	O
also	O
supported	O
,	O
providing	O
the	O
ability	O
for	O
interfacing	O
with	O
PCI	O
Express-based	O
storage	O
devices	O
.	O
</s>
<s>
Each	O
of	O
the	O
X99	B-Device
's	O
SATA	B-Architecture
Express	I-Architecture
ports	O
requires	O
two	O
PCI	O
Express2.0	O
lanes	O
provided	O
by	O
the	O
chipset	O
,	O
while	O
the	O
M.2	B-Protocol
slots	I-Protocol
can	O
use	O
either	O
two	O
2.0	O
lanes	O
from	O
the	O
chipset	O
itself	O
,	O
or	O
up	O
to	O
four	O
3.0	O
lanes	O
taken	O
directly	O
from	O
the	O
processor	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
the	O
X99	B-Device
provides	O
bandwidths	O
of	O
up	O
to	O
3.94GB/s	O
for	O
connected	O
PCI	O
Express	O
storage	O
devices	O
.	O
</s>
<s>
One	O
Extensible	O
Host	O
Controller	O
Interface	O
(	O
xHCI	O
)	O
controller	O
and	O
two	O
Enhanced	O
Host	O
Controller	O
Interface	O
(	O
EHCI	O
)	O
controllers	O
are	O
integrated	O
into	O
the	O
X99	B-Device
chipset	O
,	O
providing	O
a	O
total	O
of	O
up	O
to	O
14	O
USB	O
ports	O
.	O
</s>
<s>
Integrated	O
Intel	O
High	O
Definition	O
Audio	O
(	O
HD	O
Audio	O
)	O
supports	O
up	O
to	O
four	O
hardware	O
audio	B-Algorithm
codecs	I-Algorithm
and	O
multi-channel	O
audio	O
streams	O
.	O
</s>
<s>
Some	O
of	O
the	O
connectivity	O
options	O
and	O
interfaces	O
provided	O
by	O
the	O
X99	B-Device
chipset	O
are	O
configurable	O
via	O
Flexible	O
I/O	O
,	O
which	O
allows	O
certain	O
hardware	O
capacities	O
of	O
the	O
chipset	O
to	O
be	O
selectively	O
distributed	O
between	O
the	O
PCI	O
Express	O
,	O
USB3.0	O
and	O
SATA	O
interfaces	O
.	O
</s>
<s>
That	O
way	O
,	O
connectivity	O
options	O
of	O
the	O
X99	B-Device
chipset	O
may	O
be	O
adjusted	O
to	O
fit	O
the	O
needs	O
of	O
a	O
particular	O
motherboard	O
implementation	O
;	O
for	O
example	O
,	O
some	O
of	O
the	O
SATA	O
or	O
USB3.0	O
ports	O
may	O
be	O
exchanged	O
for	O
additional	O
PCI	O
Express2.0	O
lanes	O
.	O
</s>
<s>
The	O
X99	B-Device
chipset	O
supports	O
Virtualization	B-General_Concept
Technology	O
for	O
Directed	O
I/O	O
(	O
Intel	O
VT-d	O
)	O
,	O
which	O
provides	O
hardware	O
support	O
for	O
virtualization	B-General_Concept
by	O
implementing	O
an	O
input/output	B-General_Concept
memory	I-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
IOMMU	B-General_Concept
)	O
.	O
</s>
<s>
The	O
chipset	O
also	O
integrates	O
a	O
Low	O
Pin	O
Count	O
(	O
LPC	O
)	O
interface	O
,	O
supporting	O
interrupt	B-Architecture
controllers	I-Architecture
,	O
timers	O
,	O
power	O
management	O
,	O
super	B-Device
I/O	I-Device
,	O
real-time	O
clock	O
(	O
RTC	O
)	O
,	O
etc	O
.	O
</s>
<s>
Integrated	O
Serial	B-Architecture
Peripheral	I-Architecture
Interface	I-Architecture
(	O
SPI	O
)	O
allows	O
interfacing	O
with	O
devices	O
such	O
as	O
Trusted	O
Platform	O
Modules	O
(	O
TPMs	O
)	O
and	O
serial	O
flash	O
devices	O
.	O
</s>
<s>
System	B-Algorithm
Management	I-Algorithm
Bus	I-Algorithm
(	O
SMBus	B-Algorithm
)	O
is	O
also	O
provided	O
,	O
with	O
additional	O
support	O
for	O
I2C	O
devices	O
.	O
</s>
<s>
Overclocking	B-Application
is	O
available	O
for	O
unlocked	O
variants	O
of	O
the	O
supported	O
processors	B-General_Concept
.	O
</s>
<s>
As	O
a	O
significant	O
new	O
feature	O
,	O
the	O
X99	B-Device
enthusiast	O
platform	O
as	O
a	O
whole	O
was	O
the	O
first	O
to	O
support	O
DDR4	O
memory	O
.	O
</s>
<s>
Thanks	O
to	O
the	O
features	O
of	O
integrated	B-General_Concept
memory	I-General_Concept
controllers	I-General_Concept
(	O
IMCs	O
)	O
of	O
supported	O
processors	B-General_Concept
,	O
the	O
X99	B-Device
platform	O
also	O
supports	O
dual	B-Architecture
-	I-Architecture
and	O
quad-channel	B-Architecture
memory	I-Architecture
layouts	O
,	O
with	O
optional	O
support	O
for	O
registered	B-General_Concept
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
