<s>
The	O
Intel	B-Device
X58	I-Device
(	O
codenamed	B-Architecture
Tylersburg	O
)	O
is	O
an	O
Intel	O
chip	O
designed	O
to	O
connect	O
Intel	O
processors	O
with	O
Intel	B-Architecture
QuickPath	I-Architecture
Interconnect	I-Architecture
(	O
QPI	B-Architecture
)	O
interface	O
to	O
peripheral	O
devices	O
.	O
</s>
<s>
Supported	O
processors	O
implement	O
the	O
Nehalem	B-Device
microarchitecture	I-Device
and	O
therefore	O
have	O
an	O
integrated	O
memory	O
controller	O
(	O
IMC	O
)	O
,	O
so	O
the	O
X58	B-Device
does	O
not	O
have	O
a	O
memory	O
interface	O
.	O
</s>
<s>
Initially	O
supported	O
processors	O
were	O
the	O
Core	B-Device
i7	I-Device
,	O
but	O
the	O
chip	O
also	O
supported	O
Nehalem	B-Device
and	O
Westmere-based	O
Xeon	B-Device
processors	O
.	O
</s>
<s>
The	O
QuickPath	B-Architecture
architecture	O
differs	O
considerably	O
from	O
earlier	O
Intel	O
architectures	O
,	O
and	O
is	O
much	O
closer	O
to	O
AMD	O
's	O
HyperTransport	B-Device
architecture	O
.	O
</s>
<s>
Except	O
for	O
the	O
lack	O
of	O
a	O
memory	O
interface	O
,	O
the	O
X58	B-Device
is	O
similar	O
to	O
the	O
traditional	O
northbridge	B-Device
:	O
it	O
communicates	O
with	O
the	O
processor(s )	O
via	O
the	O
high	O
bandwidth	O
QuickPath	B-Architecture
Interconnect	I-Architecture
,	O
it	O
communicates	O
with	O
the	O
southbridge	B-Device
via	O
Direct	B-Architecture
Media	I-Architecture
Interface	I-Architecture
(	O
DMI	B-Architecture
)	O
,	O
and	O
it	O
communicates	O
with	O
high	O
bandwidth	O
peripherals	O
via	O
PCI	O
Express	O
(	O
PCIe	O
)	O
.	O
</s>
<s>
The	O
X58	B-Device
is	O
not	O
a	O
memory	B-Device
controller	I-Device
hub	I-Device
(	O
MCH	O
)	O
,	O
because	O
it	O
has	O
no	O
memory	O
interface	O
,	O
so	O
Intel	O
calls	O
it	O
an	O
I/O	O
hub	O
.	O
</s>
<s>
This	O
should	O
not	O
be	O
confused	O
with	O
the	O
similar	O
term	O
I/O	B-Device
controller	I-Device
hub	I-Device
(	O
ICH	B-Device
)	O
which	O
has	O
traditionally	O
been	O
used	O
to	O
refer	O
to	O
the	O
southbridge	B-Device
chips	O
.	O
</s>
<s>
Intel	O
documentation	O
now	O
refers	O
to	O
the	O
southbridge	B-Device
as	O
the	O
Legacy	O
I/O	B-Device
Controller	I-Device
Hub	I-Device
.	O
</s>
<s>
The	O
X58	B-Device
has	O
36	O
PCIe	O
lanes	O
that	O
are	O
arranged	O
in	O
two	O
×16	O
links	O
,	O
DMI	B-Architecture
link	O
and	O
"	O
spare	O
"	O
-based	O
link	O
.	O
</s>
<s>
When	O
used	O
with	O
the	O
ICH10	O
I/O	B-Device
Controller	I-Device
Hub	I-Device
with	O
×4	O
DMI	B-Architecture
connection	O
the	O
"	O
spare	O
"	O
supports	O
a	O
separate	O
×4	O
PCIe	O
connection	O
.	O
</s>
<s>
Future	O
southbridge	B-Device
chips	O
DMI	B-Architecture
may	O
support	O
a	O
wider	O
DMI	B-Architecture
.	O
</s>
<s>
Each	O
X58	B-Device
QuickPath	B-Architecture
Interconnect	I-Architecture
uses	O
21	O
unidirectional	O
differential	O
pairs	O
in	O
each	O
direction	O
,	O
for	O
a	O
total	O
of	O
84	O
pins	O
per	O
QPI	B-Architecture
.	O
</s>
<s>
At	O
the	O
highest	O
bandwidth	O
,	O
each	O
QPI	B-Architecture
can	O
transfer	O
up	O
to	O
12.8	O
GB/s	O
usable	O
in	O
each	O
direction	O
simultaneously	O
using	O
the	O
QPI	B-Architecture
protocol	O
.	O
</s>
<s>
The	O
protocol	O
transfers	O
information	O
in	O
80	O
bit	O
flits	B-Protocol
which	O
contain	O
8	O
bits	O
of	O
error	O
correction	O
,	O
8	O
bits	O
of	O
QPI	B-Architecture
routing	O
information	O
,	O
and	O
64	O
bits	O
of	O
data	O
.	O
</s>
<s>
X58	B-Device
PCIe	O
ports	O
support	O
full	O
PCIe	O
2.0	O
bandwidth	O
(	O
e.g.	O
,	O
up	O
to	O
8GB/s	O
including	O
overheads	O
per	O
×16	O
link	O
)	O
and	O
each	O
×16	O
link	O
may	O
be	O
divided	O
into	O
total	O
16	O
lanes	O
in	O
any	O
combination	O
of	O
×8	O
,	O
×4	O
,	O
×2	O
or	O
×1	O
ports	O
.	O
</s>
<s>
Unlike	O
the	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
,	O
QPI	B-Architecture
is	O
a	O
point-to-point	O
interface	O
and	O
supports	O
not	O
only	O
processor-chipset	O
interface	O
,	O
but	O
also	O
processor-to-processor	O
connection	O
and	O
chip-to-chip	O
connection	O
.	O
</s>
<s>
The	O
X58	B-Device
has	O
two	O
QPIs	B-Architecture
and	O
can	O
directly	O
connect	O
to	O
two	O
processors	O
on	O
a	O
multi-socket	O
motherboard	O
or	O
form	O
a	O
ring-like	O
connection	O
(	O
processor	O
1	O
to	O
X58	B-Device
to	O
processor	O
2	O
back	O
to	O
processor	O
1	O
)	O
.	O
</s>
<s>
When	O
used	O
with	O
the	O
Intel	B-Device
Core	I-Device
i7	I-Device
,	O
the	O
second	O
QPI	B-Architecture
is	O
usually	O
unused	O
(	O
though	O
,	O
in	O
principle	O
,	O
the	O
second	O
X58	B-Device
might	O
be	O
daisy-chained	O
on	O
the	O
board	O
)	O
.	O
</s>
<s>
When	O
used	O
with	O
the	O
"	O
Gainestown	O
"	O
DP	O
processor	O
,	O
which	O
will	O
have	O
two	O
QPIs	B-Architecture
,	O
the	O
X58	B-Device
and	O
the	O
two	O
processors	O
may	O
be	O
connected	O
in	O
a	O
triangle	O
or	O
ring	O
.	O
</s>
<s>
For	O
MP	O
processors	O
such	O
as	O
"	O
Beckton	O
"	O
with	O
more	O
than	O
two	O
QPIs	B-Architecture
,	O
the	O
X58	B-Device
is	O
either	O
connected	O
to	O
two	O
processors	O
,	O
which	O
in	O
turn	O
are	O
connected	O
in	O
a	O
"	O
mesh	O
"	O
of	O
QPIs	B-Architecture
to	O
other	O
processors	O
or	O
attached	O
"	O
in	O
pairs	O
"	O
to	O
two	O
different	O
processors	O
.	O
</s>
<s>
I/O	O
for	O
"	O
remote	O
"	O
processors	O
is	O
relayed	O
via	O
the	O
inter-processors	O
QPI	B-Architecture
.	O
</s>
<s>
X58	B-Device
board	O
manufacturers	O
can	O
build	O
SLI-compatible	O
Intel	B-Device
chipset	I-Device
boards	O
by	O
submitting	O
their	O
designs	O
to	O
nVidia	O
for	O
validation	O
.	O
</s>
<s>
However	O
,	O
users	O
wishing	O
to	O
run	O
more	O
than	O
two	O
Nvidia	O
video	O
cards	O
in	O
PCIe	O
×16	O
will	O
still	O
need	O
to	O
purchase	O
motherboards	O
equipped	O
with	O
one	O
or	O
more	O
nVidia	B-Device
nForce	I-Device
chipsets	I-Device
.	O
</s>
<s>
It	O
is	O
still	O
possible	O
to	O
run	O
more	O
than	O
two	O
video	O
cards	O
in	O
an	O
SLI-configuration	O
at	O
fewer	O
PCIe	O
lane	O
widths	O
.	O
</s>
<s>
The	O
X58	B-Device
chipset	O
itself	O
supports	O
up	O
to	O
36	O
PCI-Express	O
2.0	O
lanes	O
,	O
so	O
it	O
is	O
possible	O
to	O
have	O
two	O
PCIe	O
×16	O
slots	O
and	O
one	O
PCIe	O
×4	O
slot	O
on	O
the	O
same	O
motherboard	O
.	O
</s>
<s>
ICH10-compatible	O
DMI	B-Architecture
.	O
</s>
