<s>
Timna	O
was	O
the	O
codename	O
of	O
a	O
proposed	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
family	O
by	O
Intel	O
.	O
</s>
<s>
The	O
project	O
was	O
announced	O
in	O
1999	O
and	O
was	O
designed	O
in	O
Haifa	B-Algorithm
,	O
Israel	O
;	O
it	O
is	O
named	O
after	O
the	O
Timna	O
Valley	O
in	O
Israel	O
.	O
</s>
<s>
The	O
chip	O
was	O
supposed	O
to	O
be	O
Intel	O
's	O
first	O
CPU	O
with	O
an	O
integrated	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
(	O
GPU	B-Architecture
)	O
and	O
random	B-Architecture
access	I-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
)	O
controller	O
which	O
was	O
designed	O
to	O
work	O
with	O
the	O
RDRAM	O
type	O
of	O
RAM	B-Architecture
.	O
</s>
<s>
It	O
was	O
decided	O
to	O
use	O
the	O
Memory	O
Translator	O
Hub	O
(	O
MTH	O
)	O
that	O
is	O
also	O
used	O
by	O
the	O
Intel	O
820	O
chipset	O
to	O
link	O
Timna	O
with	O
the	O
SDRAM	O
type	O
of	O
RAM	B-Architecture
.	O
</s>
<s>
The	O
GPU	B-Architecture
(	O
codenamed	O
Capitola	O
)	O
that	O
was	O
to	O
be	O
used	O
in	O
conjunction	O
with	O
Timna	O
was	O
based	O
on	O
i752/i754	O
that	O
were	O
used	O
with	O
810/815E	O
chipsets	O
.	O
</s>
<s>
The	O
processor	O
was	O
expected	O
to	O
be	O
clocked	O
from	O
600MHz	O
to	O
700MHz	O
,	O
use	O
a	O
133MHz	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
,	O
have	O
a	O
L2	O
cache	O
size	O
of	O
128	O
KB	O
,	O
and	O
was	O
to	O
be	O
manufactured	O
at	O
a	O
180nm	O
process	O
.	O
</s>
<s>
Intel	O
Haifa	B-Algorithm
was	O
later	O
tasked	O
to	O
be	O
the	O
backup	O
team	O
for	O
Intel	O
's	O
mobile	O
CPU	O
design	O
.	O
</s>
<s>
Their	O
knowledge	O
of	O
Timna	O
's	O
P6	B-Device
derived	O
architecture	O
heavily	O
influenced	O
their	O
project	O
Banias	O
.	O
</s>
