<s>
The	O
Intel	B-Architecture
QuickPath	I-Architecture
Interconnect	I-Architecture
(	O
QPI	B-Architecture
)	O
is	O
a	O
point-to-point	O
processor	B-Architecture
interconnect	B-Protocol
developed	O
by	O
Intel	O
which	O
replaced	O
the	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
in	O
Xeon	B-Device
,	O
Itanium	B-General_Concept
,	O
and	O
certain	O
desktop	O
platforms	O
starting	O
in	O
2008	O
.	O
</s>
<s>
Prior	O
to	O
the	O
name	O
's	O
announcement	O
,	O
Intel	O
referred	O
to	O
it	O
as	O
Common	B-Architecture
System	I-Architecture
Interface	I-Architecture
(	O
CSI	O
)	O
.	O
</s>
<s>
QPI	B-Architecture
1.1	O
is	O
a	O
significantly	O
revamped	O
version	O
introduced	O
with	O
Sandy	B-Device
Bridge-EP	I-Device
(	O
Romley	B-Device
platform	O
)	O
.	O
</s>
<s>
QPI	B-Architecture
was	O
replaced	O
by	O
Intel	B-Architecture
Ultra	I-Architecture
Path	I-Architecture
Interconnect	I-Architecture
(	O
UPI	O
)	O
in	O
Skylake-SP	O
Xeon	B-Device
processors	O
based	O
on	O
LGA	B-Device
3647	I-Device
socket	O
.	O
</s>
<s>
Although	O
sometimes	O
called	O
a	O
"	O
bus	O
"	O
,	O
QPI	B-Architecture
is	O
a	O
point-to-point	O
interconnect	B-Protocol
.	O
</s>
<s>
It	O
was	O
designed	O
to	O
compete	O
with	O
HyperTransport	B-Device
that	O
had	O
been	O
used	O
by	O
Advanced	O
Micro	O
Devices	O
(	O
AMD	O
)	O
since	O
around	O
2003	O
.	O
</s>
<s>
Intel	O
developed	O
QPI	B-Architecture
at	O
its	O
Massachusetts	O
Microprocessor	B-Architecture
Design	O
Center	O
(	O
MMDC	O
)	O
by	O
members	O
of	O
what	O
had	O
been	O
the	O
Alpha	B-Device
Development	O
Group	O
,	O
which	O
Intel	O
had	O
acquired	O
from	O
Compaq	O
and	O
HP	O
and	O
in	O
turn	O
originally	O
came	O
from	O
Digital	O
Equipment	O
Corporation	O
(	O
DEC	O
)	O
.	O
</s>
<s>
Intel	O
first	O
delivered	O
it	O
for	O
desktop	O
processors	O
in	O
November	O
2008	O
on	O
the	O
Intel	B-Device
Core	I-Device
i7-9xx	I-Device
and	O
X58	B-Device
chipset	B-Device
.	O
</s>
<s>
It	O
was	O
released	O
in	O
Xeon	B-Device
processors	O
code-named	O
Nehalem	B-Device
in	O
March	O
2009	O
and	O
Itanium	B-General_Concept
processors	O
in	O
February	O
2010	O
(	O
code	O
named	O
Tukwila	O
)	O
.	O
</s>
<s>
It	O
was	O
supplanted	O
by	O
the	O
Intel	B-Architecture
Ultra	I-Architecture
Path	I-Architecture
Interconnect	I-Architecture
starting	O
in	O
2017	O
on	O
the	O
Xeon	B-Device
Skylake-SP	O
platforms	O
.	O
</s>
<s>
The	O
QPI	B-Architecture
is	O
an	O
element	O
of	O
a	O
system	O
architecture	O
that	O
Intel	O
calls	O
the	O
QuickPath	B-Architecture
architecture	O
that	O
implements	O
what	O
Intel	O
calls	O
QuickPath	B-Architecture
technology	O
.	O
</s>
<s>
In	O
its	O
simplest	O
form	O
on	O
a	O
single-processor	O
motherboard	O
,	O
a	O
single	O
QPI	B-Architecture
is	O
used	O
to	O
connect	O
the	O
processor	B-Architecture
to	O
the	O
IO	O
Hub	O
(	O
e.g.	O
,	O
to	O
connect	O
an	O
Intel	B-Device
Core	I-Device
i7	I-Device
to	O
an	O
X58	B-Device
)	O
.	O
</s>
<s>
In	O
more	O
complex	O
instances	O
of	O
the	O
architecture	O
,	O
separate	O
QPI	B-Architecture
link	O
pairs	O
connect	O
one	O
or	O
more	O
processors	O
and	O
one	O
or	O
more	O
IO	O
hubs	O
or	O
routing	O
hubs	O
in	O
a	O
network	O
on	O
the	O
motherboard	O
,	O
allowing	O
all	O
of	O
the	O
components	O
to	O
access	O
other	O
components	O
via	O
the	O
network	O
.	O
</s>
<s>
As	O
with	O
HyperTransport	B-Device
,	O
the	O
QuickPath	B-Architecture
Architecture	O
assumes	O
that	O
the	O
processors	O
will	O
have	O
integrated	B-General_Concept
memory	I-General_Concept
controllers	I-General_Concept
,	O
and	O
enables	O
a	O
non-uniform	B-Operating_System
memory	I-Operating_System
access	I-Operating_System
(	O
NUMA	O
)	O
architecture	O
.	O
</s>
<s>
Each	O
QPI	B-Architecture
comprises	O
two	O
20-lane	O
point-to-point	O
data	O
links	O
,	O
one	O
in	O
each	O
direction	O
(	O
full	O
duplex	O
)	O
,	O
with	O
a	O
separate	O
clock	O
pair	O
in	O
each	O
direction	O
,	O
for	O
a	O
total	O
of	O
42	O
signals	O
.	O
</s>
<s>
The	O
basic	O
unit	O
of	O
transfer	O
is	O
the	O
80-bit	O
flit	B-Protocol
,	O
which	O
has	O
8	O
bits	O
for	O
error	O
detection	O
,	O
8	O
bits	O
for	O
"	O
link-layer	O
header	O
"	O
,	O
and	O
64	O
bits	O
for	O
data	O
.	O
</s>
<s>
One	O
80-bit	O
flit	B-Protocol
is	O
transferred	O
in	O
two	O
clock	O
cycles	O
(	O
four	O
20-bit	O
transfers	O
,	O
two	O
per	O
clock	O
tick	O
.	O
)	O
</s>
<s>
QPI	B-Architecture
bandwidths	O
are	O
advertised	O
by	O
computing	O
the	O
transfer	O
of	O
64	O
bits	O
(	O
8	O
bytes	O
)	O
of	O
data	O
every	O
two	O
clock	O
cycles	O
in	O
each	O
direction	O
.	O
</s>
<s>
Although	O
the	O
initial	O
implementations	O
use	O
single	O
four-quadrant	O
links	O
,	O
the	O
QPI	B-Architecture
specification	O
permits	O
other	O
implementations	O
.	O
</s>
<s>
On	O
high-reliability	O
servers	O
,	O
a	O
QPI	B-Architecture
link	O
can	O
operate	O
in	O
a	O
degraded	O
mode	O
.	O
</s>
<s>
The	O
initial	O
Nehalem	B-Device
implementation	O
used	O
a	O
full	O
four-quadrant	O
interface	O
to	O
achieve	O
25.6GB/s	O
,	O
which	O
provides	O
exactly	O
double	O
the	O
theoretical	O
bandwidth	O
of	O
Intel	O
's	O
1600MHz	O
FSB	O
used	O
in	O
the	O
X48	O
chipset	B-Device
.	O
</s>
<s>
Although	O
some	O
high-end	O
Core	B-Device
i7	I-Device
processors	O
expose	O
QPI	B-Architecture
,	O
other	O
"	O
mainstream	O
"	O
Nehalem	B-Device
desktop	O
and	O
mobile	O
processors	O
intended	O
for	O
single-socket	O
boards	O
(	O
e.g.	O
</s>
<s>
LGA	B-Device
1156	I-Device
Core	O
i3	O
,	O
Core	O
i5	O
,	O
and	O
other	O
Core	B-Device
i7	I-Device
processors	O
from	O
the	O
Lynnfield/Clarksfield	O
and	O
successor	O
families	O
)	O
do	O
not	O
expose	O
QPI	B-Architecture
externally	O
,	O
because	O
these	O
processors	O
are	O
not	O
intended	O
to	O
participate	O
in	O
multi-socket	O
systems	O
.	O
</s>
<s>
However	O
,	O
QPI	B-Architecture
is	O
used	O
internally	O
on	O
these	O
chips	O
to	O
communicate	O
with	O
the	O
"	O
uncore	B-General_Concept
"	O
,	O
which	O
is	O
part	O
of	O
the	O
chip	O
containing	O
memory	B-General_Concept
controllers	I-General_Concept
,	O
CPU-side	O
PCI	O
Express	O
and	O
GPU	O
,	O
if	O
present	O
;	O
the	O
uncore	B-General_Concept
may	O
or	O
may	O
not	O
be	O
on	O
the	O
same	O
die	O
as	O
the	O
CPU	O
core	O
,	O
for	O
instance	O
it	O
is	O
on	O
a	O
separate	O
die	O
in	O
the	O
Westmere-based	O
Clarkdale/Arrandale	O
.	O
</s>
<s>
In	O
post-2009	O
single-socket	O
chips	O
starting	O
with	O
Lynnfield	B-Device
,	O
Clarksfield	B-Device
,	O
Clarkdale	B-Device
and	O
Arrandale	O
,	O
the	O
traditional	O
northbridge	B-Device
functions	O
are	O
integrated	O
into	O
these	O
processors	O
,	O
which	O
therefore	O
communicate	O
externally	O
via	O
the	O
slower	O
DMI	B-Architecture
and	O
PCI	O
Express	O
interfaces	O
.	O
</s>
<s>
Thus	O
,	O
there	O
is	O
no	O
need	O
to	O
incur	O
the	O
expense	O
of	O
exposing	O
the	O
(	O
former	O
)	O
front-side	B-Architecture
bus	I-Architecture
interface	O
via	O
the	O
processor	B-Architecture
socket	O
.	O
</s>
<s>
Although	O
the	O
core	O
–	O
uncore	B-General_Concept
QPI	B-Architecture
link	O
is	O
not	O
present	O
in	O
desktop	O
and	O
mobile	O
Sandy	B-Device
Bridge	I-Device
processors	O
(	O
as	O
it	O
was	O
on	O
Clarkdale	B-Device
,	O
for	O
example	O
)	O
,	O
the	O
internal	O
ring	O
interconnect	B-Protocol
between	O
on-die	O
cores	O
is	O
also	O
based	O
on	O
the	O
principles	O
behind	O
QPI	B-Architecture
,	O
at	O
least	O
as	O
far	O
as	O
cache	B-General_Concept
coherency	I-General_Concept
is	O
concerned	O
.	O
</s>
<s>
Being	O
a	O
synchronous	B-Application
circuit	I-Application
the	O
QPI	B-Architecture
operates	O
at	O
a	O
clock	O
rate	O
of	O
2.4GHz	O
,	O
2.93GHz	O
,	O
3.2GHz	O
,	O
3.6GHz	O
,	O
4.0GHz	O
or	O
4.8GHz	O
(	O
3.6GHz	O
and	O
4.0GHz	O
frequencies	O
were	O
introduced	O
with	O
the	O
Sandy	O
Bridge-E/EP	O
platform	O
and	O
4.8GHz	O
with	O
the	O
Haswell-E/EP	O
platform	O
)	O
.	O
</s>
<s>
The	O
non-extreme	O
Core	B-Device
i7	I-Device
9xx	O
processors	O
are	O
restricted	O
to	O
a	O
2.4GHz	O
frequency	O
at	O
stock	O
reference	O
clocks	O
.	O
</s>
<s>
Intel	O
describes	O
the	O
data	O
throughput	O
(	O
in	O
GB/s	O
)	O
by	O
counting	O
only	O
the	O
64-bit	O
data	O
payload	O
in	O
each	O
80-bit	O
flit	B-Protocol
.	O
</s>
<s>
Thus	O
,	O
Intel	O
describes	O
a	O
20-lane	O
QPI	B-Architecture
link	O
pair	O
(	O
send	O
and	O
receive	O
)	O
with	O
a	O
3.2GHz	O
clock	O
as	O
having	O
a	O
data	O
rate	O
of	O
25.6GB/s	O
.	O
</s>
<s>
More	O
generally	O
,	O
by	O
this	O
definition	O
a	O
two-link	O
20-lane	O
QPI	B-Architecture
transfers	O
eight	O
bytes	O
per	O
clock	O
cycle	O
,	O
four	O
in	O
each	O
direction	O
.	O
</s>
<s>
QPI	B-Architecture
is	O
specified	O
as	O
a	O
five-layer	O
architecture	O
,	O
with	O
separate	O
physical	O
,	O
link	O
,	O
routing	O
,	O
transport	O
,	O
and	O
protocol	O
layers	O
.	O
</s>
<s>
In	O
devices	O
intended	O
only	O
for	O
point-to-point	O
QPI	B-Architecture
use	O
with	O
no	O
forwarding	O
,	O
such	O
as	O
the	O
Core	O
i7-9xx	O
and	O
Xeon	B-Device
DP	O
processors	O
,	O
the	O
transport	O
layer	O
is	O
not	O
present	O
and	O
the	O
routing	O
layer	O
is	O
minimal	O
.	O
</s>
<s>
The	O
physical	O
layer	O
transmits	O
a	O
20-bit	O
"	O
phit	O
"	O
using	O
a	O
single	O
clock	O
edge	O
on	O
20	O
lanes	O
when	O
all	O
20	O
lanes	O
are	O
available	O
,	O
or	O
on	O
10	O
or	O
5	O
lanes	O
when	O
the	O
QPI	B-Architecture
is	O
reconfigured	O
due	O
to	O
a	O
failure	O
.	O
</s>
<s>
The	O
link	O
layer	O
is	O
responsible	O
for	O
sending	O
and	O
receiving	O
80-bit	O
flits	B-Protocol
.	O
</s>
<s>
Each	O
flit	B-Protocol
is	O
sent	O
to	O
the	O
physical	O
layer	O
as	O
four	O
20-bit	O
phits	O
.	O
</s>
<s>
Each	O
flit	B-Protocol
contains	O
an	O
8-bit	O
CRC	O
generated	O
by	O
the	O
link	O
layer	O
transmitter	O
and	O
a	O
72-bit	O
payload	O
.	O
</s>
<s>
If	O
the	O
link	O
layer	O
receiver	O
detects	O
a	O
CRC	O
error	O
,	O
the	O
receiver	O
notifies	O
the	O
transmitter	O
via	O
a	O
flit	B-Protocol
on	O
the	O
return	O
link	O
of	O
the	O
pair	O
and	O
the	O
transmitter	O
resends	O
the	O
flit	B-Protocol
.	O
</s>
<s>
The	O
link	O
layer	O
supports	O
six	O
different	O
classes	O
of	O
message	O
to	O
permit	O
the	O
higher	O
layers	O
to	O
distinguish	O
data	O
flits	B-Protocol
from	O
non-data	O
messages	O
primarily	O
for	O
maintenance	O
of	O
cache	B-General_Concept
coherence	I-General_Concept
.	O
</s>
<s>
In	O
complex	O
implementations	O
of	O
the	O
QuickPath	B-Architecture
architecture	O
,	O
the	O
link	O
layer	O
can	O
be	O
configured	O
to	O
maintain	O
separate	O
flows	O
and	O
flow	O
control	O
for	O
the	O
different	O
classes	O
.	O
</s>
<s>
It	O
is	O
not	O
clear	O
if	O
this	O
is	O
needed	O
or	O
implemented	O
for	O
single-processor	O
and	O
dual-processor	O
implementations	O
.	O
</s>
<s>
If	O
not	O
,	O
it	O
is	O
sent	O
on	O
the	O
correct	O
outbound	O
QPI	B-Architecture
.	O
</s>
<s>
On	O
a	O
device	O
with	O
only	O
one	O
QPI	B-Architecture
,	O
the	O
routing	O
layer	O
is	O
minimal	O
.	O
</s>
<s>
For	O
more	O
complex	O
implementations	O
,	O
the	O
routing	O
layer	O
's	O
routing	O
tables	O
are	O
more	O
complex	O
,	O
and	O
are	O
modified	O
dynamically	O
to	O
avoid	O
failed	O
QPI	B-Architecture
links	O
.	O
</s>
<s>
This	O
includes	O
the	O
Core	B-Device
i7	I-Device
.	O
</s>
<s>
The	O
transport	O
layer	O
sends	O
and	O
receives	O
data	O
across	O
the	O
QPI	B-Architecture
network	O
from	O
its	O
peers	O
on	O
other	O
devices	O
that	O
may	O
not	O
be	O
directly	O
connected	O
(	O
i.e.	O
,	O
the	O
data	O
may	O
have	O
been	O
routed	O
through	O
an	O
intervening	O
device	O
.	O
)	O
</s>
<s>
The	O
protocol	O
layer	O
also	O
participates	O
in	O
maintenance	O
of	O
cache	B-General_Concept
coherence	I-General_Concept
by	O
sending	O
and	O
receiving	O
relevant	O
messages	O
.	O
</s>
