<s>
Intel	B-Device
microcode	I-Device
is	O
microcode	B-Device
that	O
runs	O
inside	O
x86	B-Operating_System
processors	O
made	O
by	O
Intel	O
.	O
</s>
<s>
Since	O
the	O
P6	B-Device
microarchitecture	I-Device
introduced	O
in	O
the	O
mid-1990s	O
,	O
the	O
microcode	B-Device
programs	O
can	O
be	O
patched	O
by	O
the	O
operating	O
system	O
or	O
BIOS	B-Operating_System
firmware	O
to	O
work	O
around	O
bugs	O
found	O
in	O
the	O
CPU	O
after	O
release	O
.	O
</s>
<s>
Intel	O
had	O
originally	O
designed	O
microcode	B-Device
updates	O
for	O
processor	O
debugging	O
under	O
its	O
design	O
for	O
testing	O
(	O
DFT	O
)	O
initiative	O
.	O
</s>
<s>
Following	O
the	O
Pentium	B-Device
FDIV	I-Device
bug	I-Device
,	O
the	O
patchable	O
microcode	B-Device
function	O
took	O
on	O
a	O
wider	O
purpose	O
to	O
allow	O
in-field	O
updating	O
without	O
needing	O
to	O
do	O
a	O
product	O
recall	O
.	O
</s>
<s>
In	O
the	O
P6	B-Device
and	O
later	O
microarchitectures	O
,	O
x86	B-Device
instructions	I-Device
are	O
internally	O
converted	O
into	O
simpler	O
RISC-style	O
micro-operations	B-General_Concept
that	O
are	O
specific	O
to	O
a	O
particular	O
processor	O
and	O
stepping	B-General_Concept
level	I-General_Concept
.	O
</s>
<s>
On	O
the	O
Intel	B-General_Concept
80486	I-General_Concept
and	O
AMD	B-Device
Am486	I-Device
there	O
are	O
approximately	O
250	O
lines	O
of	O
microcode	B-Device
,	O
totalling	O
12,032	O
bits	O
stored	O
in	O
the	O
microcode	B-Device
ROM	B-Device
.	O
</s>
<s>
On	O
the	O
Pentium	B-Device
Pro	I-Device
,	O
each	O
micro-operation	B-General_Concept
is	O
72-bits	O
wide	O
,	O
or	O
118-bits	O
wide	O
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
is	O
able	O
to	O
detect	O
parity	B-Error_Name
errors	I-Error_Name
in	O
its	O
internal	O
microcode	B-Device
and	O
report	O
these	O
via	O
the	O
Machine	B-Device
Check	I-Device
Architecture	I-Device
.	O
</s>
<s>
Micro-operations	B-General_Concept
have	O
a	O
consistent	O
format	O
with	O
up	O
to	O
three	O
source	O
inputs	O
,	O
and	O
two	O
destination	O
outputs	O
.	O
</s>
<s>
The	O
processor	O
performs	O
register	B-Architecture
renaming	I-Architecture
to	O
map	O
these	O
inputs	O
to	O
and	O
from	O
the	O
real	O
register	B-General_Concept
file	I-General_Concept
(	O
RRF	O
)	O
before	O
and	O
after	O
their	O
execution	O
.	O
</s>
<s>
Out-of-order	B-General_Concept
execution	I-General_Concept
is	O
used	O
,	O
so	O
the	O
micro-operations	B-General_Concept
and	O
instructions	O
they	O
represent	O
may	O
not	O
appear	O
in	O
the	O
same	O
order	O
.	O
</s>
<s>
During	O
development	O
of	O
the	O
Pentium	B-Device
Pro	I-Device
,	O
several	O
microcode	B-Device
fixes	O
were	O
included	O
between	O
the	O
A2	O
and	O
B0	O
steppings	B-General_Concept
.	O
</s>
<s>
For	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
(	O
based	O
on	O
the	O
P6	B-Device
Pentium	B-Device
Pro	I-Device
)	O
,	O
additional	O
micro-operations	B-General_Concept
were	O
added	O
to	O
support	O
the	O
MMX	B-Architecture
instruction	I-Architecture
set	I-Architecture
.	O
</s>
<s>
In	O
several	O
cases	O
,	O
"	O
microcode	B-Device
assists	O
"	O
were	O
added	O
to	O
handle	O
rare	O
corner-cases	O
in	O
a	O
reliable	O
way	O
.	O
</s>
<s>
The	O
Pentium	O
4	O
can	O
have	O
126	O
micro-operations	B-General_Concept
in	O
flight	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
Micro-operations	B-General_Concept
are	O
decoded	O
and	O
stored	O
in	O
an	O
Execution	O
Trace	O
Cache	O
with	O
12,000	O
entries	O
,	O
to	O
avoid	O
repeated	O
decoding	O
of	O
the	O
same	O
x86	B-Device
instructions	I-Device
.	O
</s>
<s>
Groups	O
of	O
six	O
micro-operations	B-General_Concept
are	O
packed	O
into	O
a	O
trace	O
line	O
.	O
</s>
<s>
Micro-operations	B-General_Concept
can	O
borrow	O
extra	O
immediate	O
data	O
space	O
within	O
the	O
same	O
cache-line	O
.	O
</s>
<s>
Complex	O
instructions	O
,	O
such	O
as	O
exception	O
handling	O
,	O
result	O
in	O
jumping	B-General_Concept
to	O
the	O
microcode	B-Device
ROM	B-Device
.	O
</s>
<s>
During	O
development	O
of	O
the	O
Pentium	O
4	O
,	O
microcode	B-Device
accounted	O
for	O
14%	O
of	O
processor	O
bugs	O
versus	O
30%	O
of	O
processor	O
bugs	O
during	O
development	O
of	O
the	O
Pentium	B-Device
Pro	I-Device
.	O
</s>
<s>
The	O
Intel	B-Device
Core	I-Device
microarchitecture	I-Device
introduced	O
in	O
2006	O
added	O
"	O
micro-operations	B-General_Concept
fusion	O
"	O
for	O
some	O
common	O
pairs	O
of	O
instructions	O
including	O
comparison	O
followed	O
by	O
a	O
jump	O
.	O
</s>
<s>
The	O
instruction	O
decoders	O
in	O
the	O
Core	O
convert	O
x86	B-Device
instructions	I-Device
into	O
microcode	B-Device
in	O
three	O
different	O
ways	O
:	O
</s>
<s>
For	O
Intel	O
's	O
hyper-threading	B-Operating_System
implementation	O
of	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
,	O
the	O
microcode	B-Device
ROM	B-Device
,	O
trace	O
cache	O
,	O
and	O
instruction	O
decoders	O
are	O
shared	O
,	O
but	O
the	O
micro-operation	B-General_Concept
queue	O
is	O
not	O
shared	O
.	O
</s>
<s>
In	O
the	O
mid-1990s	O
,	O
a	O
facility	O
for	O
supplying	O
new	O
microcode	B-Device
was	O
initially	O
referred	O
to	O
as	O
the	O
Pentium	B-Device
Pro	I-Device
BIOS	B-Operating_System
Update	O
Feature	O
.	O
</s>
<s>
It	O
was	O
intended	O
that	O
user-mode	B-Operating_System
applications	O
should	O
make	O
a	O
BIOS	B-Device
interrupt	I-Device
call	I-Device
to	O
supply	O
a	O
new	O
"	O
BIOS	B-Operating_System
Update	O
Data	O
Block	O
"	O
,	O
which	O
the	O
BIOS	B-Operating_System
would	O
partially	O
validate	O
and	O
save	O
to	O
nonvolatile	B-Device
BIOS	I-Device
memory	I-Device
;	O
this	O
could	O
be	O
supplied	O
to	O
the	O
installed	O
processors	O
on	O
next	O
boot	O
.	O
</s>
<s>
Intel	O
distributed	O
a	O
program	O
called	O
BUP_UTIL.EXE	O
,	O
renamed	O
CHECKUP3.EXE	O
that	O
could	O
be	O
run	O
under	O
DOS	B-Device
.	O
</s>
<s>
Collections	O
of	O
multiple	O
microcode	B-Device
updates	O
were	O
concatenated	O
together	O
and	O
numerically	O
numbered	O
with	O
the	O
extension	O
.PDB	O
,	O
such	O
as	O
PEP6.PDB	O
.	O
</s>
<s>
The	O
processor	O
boots	O
up	O
using	O
a	O
set	O
of	O
microcode	B-Device
held	O
inside	O
the	O
processor	O
and	O
stored	O
in	O
an	O
internal	O
ROM	B-Device
.	O
</s>
<s>
A	O
microcode	B-Device
update	O
populates	O
a	O
separate	O
SRAM	B-Architecture
and	O
set	O
of	O
"	O
match	O
registers	O
"	O
that	O
act	O
as	O
breakpoints	O
within	O
the	O
microcode	B-Device
ROM	B-Device
,	O
to	O
allow	O
jumping	B-General_Concept
to	O
the	O
updated	O
list	O
of	O
micro-operations	B-General_Concept
in	O
the	O
SRAM	B-Architecture
.	O
</s>
<s>
A	O
match	O
is	O
performed	O
between	O
the	O
Microcode	B-Device
Instruction	O
Pointer	O
(	O
UIP	O
)	O
all	O
of	O
the	O
match	O
registers	O
,	O
with	O
any	O
match	O
resulting	O
in	O
a	O
jump	O
to	O
the	O
corresponding	O
destination	O
microcode	B-Device
address	O
.	O
</s>
<s>
In	O
the	O
original	O
P6	B-Device
architecture	O
there	O
is	O
space	O
in	O
the	O
SRAM	B-Architecture
for	O
60	O
micro-operations	B-General_Concept
,	O
and	O
multiple	O
match/destination	O
register	O
pairs	O
.	O
</s>
<s>
It	O
takes	O
one	O
processor	O
instruction	B-General_Concept
cycle	I-General_Concept
to	O
jump	O
from	O
ROM	B-Device
microcode	B-Device
to	O
patched	O
microcode	B-Device
held	O
in	O
SRAM	B-Architecture
.	O
</s>
<s>
Match	O
registers	O
consist	O
of	O
a	O
microcode	B-Device
match	O
address	O
,	O
and	O
a	O
microcode	B-Device
destination	O
address	O
.	O
</s>
<s>
The	O
processor	O
must	O
be	O
in	O
protection	B-Operating_System
ring	I-Operating_System
zero	O
(""	O
)	O
in	O
order	O
to	O
initiate	O
a	O
microcode	B-Device
update	O
.	O
</s>
<s>
Each	O
CPU	O
in	O
a	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
arrangement	O
needs	O
to	O
be	O
updated	O
individually	O
.	O
</s>
<s>
An	O
update	O
is	O
initiated	O
by	O
placing	O
its	O
address	O
in	O
eax	O
register	O
,	O
setting	O
ecx	O
=	O
0x79	O
,	O
and	O
executing	O
a	O
wrmsr	B-General_Concept
(	O
Write	O
model-specific	B-General_Concept
register	I-General_Concept
)	O
.	O
</s>
<s>
Intel	O
distributes	O
microcode	B-Device
updates	O
as	O
a	O
2,048	O
(	O
2	O
kilobyte	O
)	O
binary	O
blob	O
.	O
</s>
<s>
The	O
update	O
contains	O
information	O
about	O
which	O
processors	O
it	O
is	O
designed	O
for	O
,	O
so	O
that	O
this	O
can	O
be	O
checked	O
against	O
the	O
result	O
of	O
the	O
CPUID	B-Architecture
instruction	O
.	O
</s>
<s>
A	O
microcode	B-Device
program	O
that	O
is	O
executed	O
by	O
the	O
processor	O
during	O
the	O
microcode	B-Device
update	O
process	O
.	O
</s>
<s>
This	O
microcode	B-Device
is	O
able	O
to	O
reconfigure	O
and	O
enable	O
or	O
disable	O
components	O
using	O
a	O
special	O
register	O
,	O
and	O
it	O
must	O
update	O
the	O
breakpoint	O
match	O
registers	O
.	O
</s>
<s>
Up	O
to	O
sixty	O
patched	O
micro-operations	B-General_Concept
to	O
be	O
populated	O
into	O
the	O
SRAM	B-Architecture
.	O
</s>
<s>
Padding	B-Algorithm
consisting	O
of	O
random	O
values	O
,	O
to	O
obfuscate	O
understanding	O
of	O
the	O
format	O
of	O
the	O
microcode	B-Device
update	O
.	O
</s>
<s>
Each	O
block	O
is	O
encoded	O
differently	O
,	O
and	O
the	O
majority	O
of	O
the	O
2,000	O
bytes	O
are	O
not	O
used	O
as	O
configuration	O
program	O
and	O
SRAM	B-Architecture
micro-operation	B-General_Concept
contents	O
themselves	O
are	O
much	O
smaller	O
.	O
</s>
<s>
Each	O
microcode	B-Device
update	O
is	O
specific	O
to	O
a	O
particular	O
CPU	O
revision	O
,	O
and	O
is	O
designed	O
to	O
be	O
rejected	O
by	O
CPUs	O
with	O
a	O
different	O
stepping	B-General_Concept
level	I-General_Concept
.	O
</s>
<s>
Microcode	B-Device
updates	O
are	O
encrypted	O
to	O
prevent	O
tampering	O
and	O
to	O
enable	O
validation	O
.	O
</s>
<s>
Microcode	B-Device
updates	O
for	O
Intel	B-Device
Atom	I-Device
,	O
Nehalem	B-Device
and	O
Sandy	B-Device
Bridge	I-Device
additionally	O
contain	O
an	O
extra	O
520-byte	O
header	O
containing	O
a	O
2048-bit	O
RSA	B-Architecture
modulus	O
with	O
an	O
exponent	O
of	O
17	O
decimal	O
.	O
</s>
<s>
Special	O
debugging-specific	O
microcode	B-Device
can	O
be	O
loaded	O
to	O
enable	O
Extended	O
Execution	O
Trace	O
,	O
which	O
then	O
outputs	O
extra	O
information	O
via	O
the	O
Breakpoint	O
Monitor	O
Pins	O
.	O
</s>
<s>
On	O
the	O
Pentium	O
4	O
,	O
loading	O
special	O
microcode	B-Device
can	O
give	O
access	O
to	O
Microcode	B-Device
Extended	O
Execution	O
Trace	O
mode	O
.	O
</s>
<s>
When	O
using	O
the	O
JTAG	O
Test	O
Access	O
Port	O
(	O
TAP	O
)	O
,	O
a	O
pair	O
of	O
Breakpoint	O
Control	O
registers	O
allow	O
breaking	O
on	O
microcode	B-Device
addresses	O
.	O
</s>
<s>
During	O
the	O
mid-1980s	O
NEC	O
and	O
Intel	O
had	O
a	O
long-running	O
US	O
federal	O
court	O
case	O
about	O
microcode	B-Device
copyright	O
.	O
</s>
<s>
NEC	O
had	O
been	O
acting	O
as	O
a	O
second	O
source	O
for	O
Intel	B-General_Concept
8086	I-General_Concept
CPUs	O
with	O
its	O
NEC	O
μPD8086	O
,	O
and	O
held	O
long-term	O
patent	O
and	O
copyright	O
cross-licensing	O
agreements	O
with	O
Intel	O
.	O
</s>
<s>
In	O
August	O
1982	O
Intel	O
sued	O
NEC	O
for	O
copyright	O
infringement	O
over	O
the	O
microcode	B-Device
implementation	O
.	O
</s>
<s>
NEC	O
prevailed	O
by	O
demonstrating	O
via	O
cleanroom	B-Application
software	I-Application
engineering	I-Application
that	O
the	O
similarities	O
in	O
the	O
implementation	O
of	O
microcode	B-Device
on	O
its	O
V20	B-Device
and	O
V30	O
processors	O
was	O
the	O
result	O
of	O
the	O
restrictions	O
demanded	O
by	O
the	O
architecture	O
,	O
rather	O
than	O
via	O
copying	O
.	O
</s>
<s>
The	O
Intel	B-General_Concept
386	I-General_Concept
can	O
perform	O
a	O
built-in	O
self-test	O
of	O
the	O
microcode	B-Device
and	O
programmable	O
logic	O
arrays	O
,	O
with	O
the	O
value	O
of	O
the	O
self-test	O
placed	O
in	O
the	O
EAX	O
register	O
.	O
</s>
<s>
During	O
the	O
BIST	O
,	O
the	O
microprogram	B-Device
counter	O
is	O
re-used	O
to	O
walk	O
through	O
all	O
of	O
the	O
ROMs	O
,	O
with	O
the	O
results	O
being	O
collated	O
via	O
a	O
network	O
of	O
multiple-input	O
signature	O
registers	O
(	O
MISRs	O
)	O
and	O
linear-feedback	O
shift	O
registers	O
.	O
</s>
<s>
On	O
start	O
up	O
of	O
the	O
Intel	B-General_Concept
486	I-General_Concept
,	O
a	O
hardware-controlled	O
BIST	O
runs	O
for	O
220	O
clock	O
cycles	O
to	O
check	O
various	O
arrays	O
including	O
the	O
microcode	B-Device
ROM	B-Device
,	O
after	O
which	O
control	O
is	O
transferred	O
to	O
the	O
microcode	B-Device
for	O
further	O
self-testing	O
of	O
registers	O
and	O
computation	O
units	O
.	O
</s>
<s>
The	O
Intel	B-General_Concept
486	I-General_Concept
microcode	B-Device
ROM	B-Device
has	O
250,000	O
transistors	O
.	O
</s>
<s>
AMD	O
had	O
a	O
long-term	O
contract	O
to	O
reuse	O
Intel	O
's	O
286	O
,	O
386	B-General_Concept
and	O
486	B-General_Concept
microcode	B-Device
.	O
</s>
<s>
In	O
October	O
2004	O
,	O
a	O
court	O
ruled	O
that	O
the	O
agreement	O
did	O
not	O
cover	O
AMD	O
distributing	O
Intel	O
's	O
486	B-General_Concept
in-circuit	B-Application
emulation	I-Application
(	O
ICE	B-Application
)	O
microcode	B-Device
.	O
</s>
<s>
In	O
May	O
2020	O
,	O
a	O
script	O
reading	O
directly	O
from	O
the	O
Control	O
Register	O
Bus	O
(	O
CRBUS	O
)	O
(	O
after	O
exploiting	O
"	O
Red	O
Unlock	O
"	O
in	O
JTAG	O
USB-A	O
to	O
USB-A	O
3.0	O
with	O
Debugging	O
Capabilities	O
,	O
without	O
D+	O
,	O
D	O
-	O
and	O
Vcc	O
)	O
was	O
used	O
to	O
read	O
from	O
the	O
Local	O
Direct	O
Access	O
Test	O
(	O
LDAT	O
)	O
port	O
of	O
the	O
Intel	O
Goldmont	B-Device
CPU	O
and	O
the	O
loaded	O
microcode	B-Device
and	O
patch	O
arrays	O
were	O
read	O
.	O
</s>
