<s>
Intel	B-Device
Ivy	I-Device
Bridge	I-Device
–	I-Device
based	I-Device
Xeon	I-Device
microprocessors	I-Device
(	O
also	O
known	O
as	O
Ivy	B-Device
Bridge-E	I-Device
)	O
is	O
the	O
follow-up	O
to	O
Sandy	B-Device
Bridge-E	I-Device
,	O
using	O
the	O
same	O
CPU	O
core	O
as	O
the	O
Ivy	B-Device
Bridge	I-Device
processor	O
,	O
but	O
in	O
LGA	B-Device
2011	I-Device
,	O
LGA	B-Device
1356	I-Device
and	O
LGA	B-Device
2011-1	I-Device
packages	O
for	O
workstations	O
and	O
servers	O
.	O
</s>
<s>
Ivy	B-Device
Bridge-E	I-Device
uses	O
LGA	B-Device
2011	I-Device
socket	O
and	O
was	O
branded	O
as	O
Core	B-Device
i7	I-Device
Extreme	O
Edition	O
and	O
Core	B-Device
i7	I-Device
high-end	O
desktop	O
(	O
HEDT	O
)	O
processors	O
,	O
despite	O
sharing	O
many	O
similarities	O
with	O
Xeon	O
E5	O
models	O
.	O
</s>
<s>
Ivy	O
Bridge-EP	O
which	O
also	O
uses	O
LGA	B-Device
2011	I-Device
socket	O
for	O
the	O
Xeon	O
E5	O
models	O
aimed	O
at	O
high-end	O
servers	O
and	O
workstations	O
.	O
</s>
<s>
Ivy	O
Bridge-EX	O
introduces	O
new	O
LGA	B-Device
2011-1	I-Device
socket	O
and	O
features	O
up	O
to	O
15	O
cores	O
.	O
</s>
<s>
Ivy	O
Bridge-EN	O
uses	O
a	O
smaller	O
LGA	B-Device
1356	I-Device
socket	O
for	O
low-end	O
and	O
dual-processor	O
servers	O
on	O
certain	O
Xeon	O
E5	O
and	O
Pentium	O
branded	O
models	O
.	O
</s>
<s>
Ivy	B-Device
Bridge	I-Device
Xeon	O
with	O
LGA	B-Device
1155	I-Device
socket	O
were	O
mostly	O
identical	O
to	O
its	O
desktop	O
counterparts	O
apart	O
from	O
the	O
missing	O
IGPU	O
despite	O
branded	O
as	O
Xeon	O
processors	O
.	O
</s>
<s>
The	O
basic	O
Ivy	B-Device
Bridge-E	I-Device
is	O
a	O
single-socket	O
processor	O
sold	O
as	O
Corei7-49xx	O
and	O
is	O
only	O
available	O
in	O
the	O
six-core	O
S1	O
stepping	B-General_Concept
,	O
with	O
some	O
versions	O
limited	O
to	O
four	O
active	O
cores	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
F16C	B-Device
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
TXT	B-Device
,	O
Intel	O
VT-x	O
,	O
Intel	O
EPT	O
,	O
Intel	O
VT-d	O
,	O
Intel	O
VT-c	O
,	O
Intel	B-Error_Name
x8	I-Error_Name
SDDC	I-Error_Name
,	O
Hyper-threading	B-Operating_System
(	O
except	O
E5-1607v2	O
,	O
E5-2603v2	O
,	O
E5-2609v2	O
and	O
E5-4627v2	O
)	O
,	O
Turbo	B-Device
Boost	I-Device
(	O
except	O
E5-1607v2	O
,	O
E5-2603v2	O
,	O
E5-2609v2	O
,	O
E5-2618Lv2	O
,	O
E5-4603v2	O
and	O
E5-4607v2	O
)	O
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
.	O
</s>
<s>
Support	O
for	O
up	O
to	O
12	O
DIMMs	B-General_Concept
of	O
DDR3	O
memory	O
per	O
CPU	O
socket	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
F16C	B-Device
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
TXT	B-Device
,	O
Intel	O
VT-x	O
,	O
Intel	O
EPT	O
,	O
Intel	O
VT-d	O
,	O
Intel	O
VT-c	O
,	O
Intel	B-Error_Name
x8	I-Error_Name
SDDC	I-Error_Name
,	O
Hyper-threading	B-Operating_System
(	O
except	O
E7-8857v2	O
)	O
,	O
Turbo	B-Device
Boost	I-Device
(	O
except	O
E7-4809v2	O
)	O
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
.	O
</s>
<s>
Support	O
for	O
up	O
to	O
24	O
DIMMs	B-General_Concept
of	O
DDR3	O
memory	O
per	O
CPU	O
socket	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
F16C	B-Device
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
TXT	B-Device
,	O
Intel	O
VT-x	O
,	O
Intel	O
EPT	O
,	O
Intel	O
VT-d	O
,	O
Intel	O
VT-c	O
,	O
Intel	B-Error_Name
x8	I-Error_Name
SDDC	I-Error_Name
,	O
Hyper-threading	B-Operating_System
(	O
except	O
E5-2403v2	O
and	O
E5-2407v2	O
)	O
,	O
Turbo	B-Device
Boost	I-Device
(	O
except	O
E5-2403v2	O
,	O
E5-2407v2	O
and	O
E5-2418Lv2	O
)	O
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
.	O
</s>
<s>
Support	O
for	O
up	O
to	O
six	O
DIMMs	B-General_Concept
of	O
DDR3	O
memory	O
per	O
CPU	O
socket	O
.	O
</s>
<s>
Intel	O
HD	O
Graphics	O
P4000	O
uses	O
drivers	O
that	O
are	O
optimized	O
and	O
certified	O
for	O
professional	O
applications	O
,	O
similar	O
to	O
nVidia	B-Application
Quadro	I-Application
and	O
AMD	B-Application
FirePro	I-Application
products	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
Streaming	B-General_Concept
SIMD	I-General_Concept
Extensions	I-General_Concept
(	O
SSE	B-General_Concept
)	O
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Advanced	B-General_Concept
Vector	I-General_Concept
Extensions	I-General_Concept
(	O
AVX	B-General_Concept
)	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Trusted	B-Device
Execution	I-Device
Technology	I-Device
(	O
TXT	B-Device
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
EPT	O
,	O
Intel	O
VT-d	O
,	O
Hyper-threading	B-Operating_System
,	O
AES-NI	B-Algorithm
.	O
</s>
