<s>
Intel	B-Application
Graphics	I-Application
Technology	I-Application
(	O
GT	O
)	O
is	O
the	O
collective	O
name	O
for	O
a	O
series	O
of	O
integrated	O
graphics	B-Architecture
processors	I-Architecture
(	O
IGPs	O
)	O
produced	O
by	O
Intel	O
that	O
are	O
manufactured	O
on	O
the	O
same	O
package	B-Algorithm
or	O
die	O
as	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	B-Device
)	O
.	O
</s>
<s>
It	O
was	O
first	O
introduced	O
in	O
2010	O
as	O
Intel	B-Application
HD	I-Application
Graphics	I-Application
and	O
renamed	O
in	O
2017	O
as	O
Intel	B-Application
UHD	I-Application
Graphics	I-Application
.	O
</s>
<s>
Intel	B-Application
Iris	I-Application
Graphics	I-Application
and	O
Intel	B-Application
Iris	I-Application
Pro	I-Application
Graphics	I-Application
are	O
the	O
IGP	O
series	O
introduced	O
in	O
2013	O
with	O
some	O
models	O
of	O
Haswell	B-Device
processors	O
as	O
the	O
high-performance	O
versions	O
of	O
HD	B-Application
Graphics	I-Application
.	O
</s>
<s>
Iris	B-Application
Pro	I-Application
Graphics	I-Application
was	O
the	O
first	O
in	O
the	O
series	O
to	O
incorporate	O
embedded	O
DRAM	O
.	O
</s>
<s>
Since	O
2016	O
Intel	O
refers	O
to	O
the	O
technology	O
as	O
Intel	B-Application
Iris	I-Application
Plus	O
Graphics	O
with	O
the	O
release	O
of	O
Kaby	B-Device
Lake	I-Device
.	O
</s>
<s>
In	O
the	O
fourth	O
quarter	O
of	O
2013	O
,	O
Intel	B-Device
integrated	I-Device
graphics	I-Device
represented	O
,	O
in	O
units	O
,	O
65%	O
of	O
all	O
PC	O
graphics	B-Architecture
processor	I-Architecture
shipments	O
.	O
</s>
<s>
However	O
,	O
this	O
percentage	O
does	O
not	O
represent	O
actual	O
adoption	O
as	O
a	O
number	O
of	O
these	O
shipped	O
units	O
end	O
up	O
in	O
systems	O
with	O
discrete	B-Device
graphics	I-Device
cards	O
.	O
</s>
<s>
Before	O
the	O
introduction	O
of	O
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
Intel	B-Device
integrated	I-Device
graphics	I-Device
were	O
built	O
into	O
the	O
motherboard	O
's	O
northbridge	B-Device
,	O
as	O
part	O
of	O
the	O
Intel	O
's	O
Hub	B-Architecture
Architecture	I-Architecture
.	O
</s>
<s>
They	O
were	O
known	O
as	O
Intel	O
Extreme	O
Graphics	O
and	O
Intel	B-Device
GMA	I-Device
.	O
</s>
<s>
As	O
part	O
of	O
the	O
Platform	B-Device
Controller	I-Device
Hub	I-Device
(	O
PCH	O
)	O
design	O
,	O
the	O
northbridge	B-Device
was	O
eliminated	O
and	O
graphics	O
processing	O
was	O
moved	O
to	O
the	O
same	O
die	O
as	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	B-Device
)	O
.	O
</s>
<s>
The	O
previous	O
Intel	B-Device
integrated	I-Device
graphics	I-Device
solution	O
,	O
Intel	B-Device
GMA	I-Device
,	O
had	O
a	O
reputation	O
of	O
lacking	O
performance	O
and	O
features	O
,	O
and	O
therefore	O
was	O
not	O
considered	O
to	O
be	O
a	O
good	O
choice	O
for	O
more	O
demanding	O
graphics	O
applications	O
,	O
such	O
as	O
3D	O
gaming	O
.	O
</s>
<s>
The	O
performance	O
increases	O
brought	O
by	O
Intel	O
's	O
HD	B-Application
Graphics	I-Application
made	O
the	O
products	O
competitive	O
with	O
integrated	O
graphics	B-Device
adapters	I-Device
made	O
by	O
its	O
rivals	O
,	O
Nvidia	O
and	O
ATI/AMD	O
.	O
</s>
<s>
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
featuring	O
minimal	O
power	O
consumption	O
that	O
is	O
important	O
in	O
laptops	B-Device
,	O
was	O
capable	O
enough	O
that	O
PC	O
manufacturers	O
often	O
stopped	O
offering	O
discrete	B-Device
graphics	I-Device
options	O
in	O
both	O
low-end	O
and	O
high-end	O
laptop	B-Device
lines	O
,	O
where	O
reduced	O
dimensions	O
and	O
low	O
power	O
consumption	O
are	O
important	O
.	O
</s>
<s>
Intel	B-Application
HD	I-Application
and	I-Application
Iris	I-Application
Graphics	I-Application
are	O
divided	O
into	O
generations	O
,	O
and	O
within	O
each	O
generation	O
are	O
divided	O
into	O
'	O
tiers	O
 '	O
of	O
increasing	O
performance	O
,	O
denominated	O
by	O
the	O
'	O
GTx	O
 '	O
label	O
.	O
</s>
<s>
Each	O
generation	O
corresponds	O
to	O
the	O
implementation	O
of	O
a	O
Gen	O
graphics	O
microarchitecture	B-General_Concept
with	O
a	O
corresponding	O
GEN	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
since	O
Gen4	O
.	O
</s>
<s>
In	O
January	O
2010	O
,	O
Clarkdale	B-Device
and	O
Arrandale	O
processors	O
with	O
Ironlake	O
graphics	O
were	O
released	O
,	O
and	O
branded	O
as	O
Celeron	B-Device
,	O
Pentium	B-General_Concept
,	O
or	O
Core	B-Device
with	O
HD	B-Application
Graphics	I-Application
.	O
</s>
<s>
Model	O
number	O
Tier	O
Execution	O
units	O
Shading	O
units	O
Base	O
clock	O
(	O
MHz	O
)	O
Boost	O
clock	O
(	O
MHz	O
)	O
GFLOPS	O
(	O
FP32	O
)	O
HD	B-Application
Graphics	I-Application
?	O
</s>
<s>
In	O
January	O
2011	O
,	O
the	O
Sandy	B-Device
Bridge	I-Device
processors	O
were	O
released	O
,	O
introducing	O
the	O
"	O
second	O
generation	O
"	O
HD	B-Application
Graphics	I-Application
:	O
</s>
<s>
Sandy	B-Device
Bridge	I-Device
Celeron	B-Device
and	O
Pentium	B-General_Concept
have	O
Intel	B-Application
HD	I-Application
,	O
while	O
Core	B-Device
i3	O
and	O
above	O
have	O
either	O
HD	O
2000	O
or	O
HD	B-Application
3000	I-Application
.	O
</s>
<s>
HD	B-Application
Graphics	I-Application
2000	I-Application
and	O
3000	O
include	O
hardware	B-Algorithm
video	I-Algorithm
encoding	I-Algorithm
and	O
HD	B-Device
postprocessing	I-Device
effects	I-Device
.	O
</s>
<s>
On	O
24	O
April	O
2012	O
,	O
Ivy	B-Device
Bridge	I-Device
was	O
released	O
,	O
introducing	O
the	O
"	O
third	O
generation	O
"	O
of	O
Intel	O
's	O
HD	B-Application
graphics	I-Application
:	O
</s>
<s>
Ivy	B-Device
Bridge	I-Device
Celeron	B-Device
and	O
Pentium	B-General_Concept
have	O
Intel	B-Application
HD	I-Application
,	O
while	O
Core	B-Device
i3	O
and	O
above	O
have	O
either	O
HD	O
2500	O
or	O
HD	O
4000	O
.	O
</s>
<s>
HD	B-Application
Graphics	I-Application
2500	I-Application
and	O
4000	O
include	O
hardware	B-Algorithm
video	I-Algorithm
encoding	I-Algorithm
and	O
HD	B-Device
postprocessing	I-Device
effects	I-Device
.	O
</s>
<s>
For	O
some	O
low-power	O
mobile	O
CPUs	B-Device
there	O
is	O
limited	O
video	B-Application
decoding	I-Application
support	O
,	O
while	O
none	O
of	O
the	O
desktop	O
CPUs	B-Device
have	O
this	O
limitation	O
.	O
</s>
<s>
HD	O
P4000	O
is	O
featured	O
on	O
the	O
Ivy	B-Device
Bridge	I-Device
E3	O
Xeon	O
processors	O
with	O
the	O
12X5	O
v2	O
descriptor	O
,	O
and	O
supports	O
unbuffered	O
ECC	O
RAM	O
.	O
</s>
<s>
In	O
June	O
2013	O
,	O
Haswell	B-Device
CPUs	B-Device
were	O
announced	O
,	O
with	O
four	O
models	O
of	O
integrated	O
GPUs	B-Architecture
:	O
</s>
<s>
The	O
128MB	O
of	O
eDRAM	O
in	O
the	O
Iris	O
Pro	O
GT3e	O
is	O
in	O
the	O
same	O
package	B-Algorithm
as	O
the	O
CPU	B-Device
,	O
but	O
on	O
a	O
separate	O
die	O
manufactured	O
in	O
a	O
different	O
process	O
.	O
</s>
<s>
Intel	O
refers	O
to	O
this	O
as	O
a	O
Level4	O
cache	O
,	O
available	O
to	O
both	O
CPU	B-Device
and	O
GPU	B-Architecture
,	O
naming	O
it	O
Crystalwell	O
.	O
</s>
<s>
In	O
November	O
2013	O
,	O
it	O
was	O
announced	O
that	O
Broadwell-K	O
desktop	O
processors	O
(	O
aimed	O
at	O
enthusiasts	O
)	O
would	O
also	O
carry	O
Iris	B-Application
Pro	I-Application
Graphics	I-Application
.	O
</s>
<s>
The	O
following	O
models	O
of	O
integrated	O
GPU	B-Architecture
are	O
announced	O
for	O
Broadwell	B-General_Concept
processors	O
:	O
</s>
<s>
The	O
Skylake	B-Architecture
line	O
of	O
processors	O
,	O
launched	O
in	O
August	O
2015	O
,	O
retires	O
VGA	B-Protocol
support	O
,	O
while	O
supporting	O
multi-monitor	B-General_Concept
setups	O
of	O
up	O
to	O
three	O
monitors	O
connected	O
via	O
HDMI1.4	O
,	O
DisplayPort1.2	O
or	O
Embedded	O
DisplayPort	B-Protocol
(	O
eDP	O
)	O
1.3	O
interfaces	O
.	O
</s>
<s>
The	O
following	O
models	O
of	O
integrated	O
GPU	B-Architecture
are	O
available	O
or	O
announced	O
for	O
the	O
Skylake	B-Architecture
processors	O
:	O
</s>
<s>
The	O
Apollo	B-Device
Lake	I-Device
line	O
of	O
processors	O
was	O
launched	O
in	O
August	O
2016	O
.	O
</s>
<s>
The	O
Kaby	B-Device
Lake	I-Device
line	O
of	O
processors	O
was	O
introduced	O
in	O
August	O
2016	O
.	O
</s>
<s>
New	O
features	O
:	O
speed	O
increases	O
,	O
support	O
for	O
4K	O
UHD	O
"	O
premium	O
"	O
(	O
DRM	O
encoded	O
)	O
streaming	O
services	O
,	O
media	O
engine	O
with	O
full	O
hardware	O
acceleration	O
of	O
8	O
-	O
and	O
10-bit	O
HEVC	B-Algorithm
and	O
VP9	B-Algorithm
decode	O
.	O
</s>
<s>
The	O
Kaby	B-Device
Lake	I-Device
Refresh	O
line	O
of	O
processors	O
was	O
introduced	O
in	O
October	O
2017	O
.	O
</s>
<s>
New	O
features	O
:	O
10nm	B-Algorithm
Gen	O
11	O
GPU	B-Architecture
microarchitecture	B-General_Concept
,	O
two	O
HEVC	B-Algorithm
10-bit	O
encode	O
pipelines	O
,	O
three	O
4K	O
display	O
pipelines	O
(	O
or	O
2×	O
5K60	O
,	O
1×	O
4K120	O
)	O
,	O
variable	O
rate	O
shading	O
(	O
VRS	O
)	O
,	O
and	O
integer	O
scaling	O
.	O
</s>
<s>
While	O
the	O
microarchitecture	B-General_Concept
continues	O
to	O
support	O
double-precision	O
floating-point	O
as	O
previous	O
versions	O
did	O
,	O
the	O
mobile	O
configurations	O
of	O
it	O
do	O
not	O
include	O
the	O
feature	O
and	O
therefore	O
on	O
these	O
it	O
is	O
supported	O
only	O
through	O
emulation	O
.	O
</s>
<s>
These	O
are	O
based	O
on	O
the	O
Intel	O
Xe-LP	O
microarchitecture	B-General_Concept
,	O
the	O
low	O
power	O
variant	O
of	O
the	O
Intel	O
Xe	O
GPU	B-Architecture
architecture	B-General_Concept
also	O
known	O
as	O
Gen	O
12	O
.	O
</s>
<s>
New	O
features	O
include	O
Sampler	O
Feedback	O
,	O
Dual	O
Queue	O
Support	O
,	O
DirectX12	O
View	O
Instancing	O
Tier2	O
,	O
and	O
AV1	B-Application
8-bit	O
and	O
10-bit	O
fixed-function	O
hardware	O
decoding	B-Application
.	O
</s>
<s>
Intel	O
Meteor	O
Lake	O
and	O
Arrow	O
Lake	O
will	O
use	O
Intel	O
Arc	O
Alchemist	O
Tile	O
GPU	B-Architecture
microarchitecture	B-General_Concept
.	O
</s>
<s>
Intel	O
Lunar	O
Lake	O
will	O
use	O
Intel	O
Arc	O
Battlemage	O
Tile	O
GPU	B-Architecture
microarchitecture	B-General_Concept
.	O
</s>
<s>
Beginning	O
with	O
Sandy	B-Device
Bridge	I-Device
,	O
the	O
graphics	B-Architecture
processors	I-Architecture
include	O
a	O
form	O
of	O
digital	O
copy	B-Application
protection	I-Application
and	O
digital	O
rights	O
management	O
(	O
DRM	O
)	O
called	O
Intel	O
Insider	O
,	O
which	O
allows	O
decryption	O
of	O
protected	O
media	O
within	O
the	O
processor	O
.	O
</s>
<s>
Intel	B-Application
Graphics	I-Application
Technology	I-Application
supports	O
the	O
HDCP	B-Protocol
technology	O
,	O
but	O
the	O
actual	O
HDCP	B-Protocol
support	O
depends	O
on	O
the	O
computer	O
's	O
motherboard	O
.	O
</s>
<s>
Intel	B-Algorithm
Quick	I-Algorithm
Sync	I-Algorithm
Video	I-Algorithm
is	O
Intel	O
's	O
hardware	B-Algorithm
video	I-Algorithm
encoding	I-Algorithm
and	O
decoding	B-Application
technology	O
,	O
which	O
is	O
integrated	O
into	O
some	O
of	O
the	O
Intel	O
CPUs	B-Device
.	O
</s>
<s>
The	O
name	O
"	O
Quick	B-Algorithm
Sync	I-Algorithm
"	O
refers	O
to	O
the	O
use	O
case	O
of	O
quickly	O
transcoding	B-Algorithm
(	O
"	O
syncing	O
"	O
)	O
a	O
video	O
from	O
,	O
for	O
example	O
,	O
a	O
DVD	O
or	O
Blu-ray	O
Disc	O
to	O
a	O
format	O
appropriate	O
to	O
,	O
for	O
example	O
,	O
a	O
smartphone	B-Application
.	O
</s>
<s>
Quick	B-Algorithm
Sync	I-Algorithm
was	O
introduced	O
with	O
the	O
Gen	O
6	O
in	O
Sandy	B-Device
Bridge	I-Device
microprocessors	O
on	O
9	O
January	O
2011	O
.	O
</s>
<s>
Graphics	O
Virtualization	O
Technology	O
(	O
GVT	O
)	O
was	O
announced	O
1	O
January	O
2014	O
and	O
introduced	O
at	O
the	O
same	O
time	O
as	O
Intel	B-Application
Iris	I-Application
Pro	O
.	O
</s>
<s>
Intel	O
integrated	O
GPUs	B-Architecture
support	O
the	O
following	O
sharing	O
methods	O
:	O
</s>
<s>
Full	O
GPU	B-Architecture
virtualization	O
in	O
hardware	O
(	O
SR-IOV	O
)	O
:	O
The	O
gpu	B-Architecture
can	O
be	O
partitioned	O
and	O
used/shared	O
by	O
multiple	O
virtual	O
machines	O
and	O
the	O
host	O
with	O
support	O
built-in	O
hardware	O
,	O
unlike	O
GVT-g	O
that	O
does	O
this	O
in	O
software(driver )	O
.	O
</s>
<s>
SR-IOV	O
(	O
Single	O
Root	O
IO	O
Virtualization	O
)	O
is	O
supported	O
only	O
on	O
platforms	O
with	O
11th	O
Generation	O
Intel®	O
Core™	O
"	O
G	O
"	O
Processors	O
(	O
products	O
formerly	O
known	O
as	O
Tiger	B-Device
Lake	I-Device
)	O
or	O
newer	O
.	O
</s>
<s>
HD2500	O
and	O
HD4000	O
GPUs	B-Architecture
in	O
Ivy	B-Device
Bridge	I-Device
CPUs	B-Device
are	O
advertised	O
as	O
supporting	O
three	O
active	O
monitors	O
,	O
but	O
this	O
only	O
works	O
if	O
two	O
of	O
the	O
monitors	O
are	O
configured	O
identically	O
,	O
which	O
covers	O
many	O
but	O
not	O
all	O
three-monitor	O
configurations	O
.	O
</s>
<s>
Using	O
two	O
or	O
three	O
DisplayPort	B-Protocol
connections	O
,	O
as	O
they	O
require	O
only	O
a	O
single	O
pixel	O
clock	O
for	O
all	O
connections	O
.	O
</s>
<s>
Passive	O
adapters	O
from	O
DisplayPort	B-Protocol
to	O
some	O
other	O
connector	O
do	O
not	O
count	O
as	O
a	O
DisplayPort	B-Protocol
connection	O
,	O
as	O
they	O
rely	O
on	O
the	O
chipset	O
being	O
able	O
to	O
emit	O
a	O
non-DisplayPort	O
signal	O
through	O
the	O
DisplayPort	B-Protocol
connector	I-Protocol
.	O
</s>
<s>
Active	O
adapters	O
that	O
contain	O
additional	O
logic	O
to	O
convert	O
the	O
DisplayPort	B-Protocol
signal	O
to	O
some	O
other	O
format	O
count	O
as	O
a	O
DisplayPort	B-Protocol
connection	O
.	O
</s>
<s>
Using	O
two	O
non-DisplayPort	O
connections	O
of	O
the	O
same	O
connection	O
type	O
(	O
for	O
example	O
,	O
two	O
HDMI	O
connections	O
)	O
and	O
the	O
same	O
clock	O
frequency	O
(	O
like	O
when	O
connected	O
to	O
two	O
identical	O
monitors	O
at	O
the	O
same	O
resolution	O
)	O
,	O
so	O
that	O
a	O
single	O
unique	O
pixel	O
clock	O
can	O
be	O
shared	O
between	O
both	O
connections	O
.	O
</s>
<s>
Another	O
possible	O
three-monitor	O
solution	O
uses	O
the	O
Embedded	O
DisplayPort	B-Protocol
on	O
a	O
mobile	O
CPU	B-Device
(	O
which	O
does	O
not	O
use	O
a	O
chipset	O
PLL	O
at	O
all	O
)	O
along	O
with	O
any	O
two	O
chipset	O
outputs	O
.	O
</s>
<s>
OpenCL	B-Application
2.1	O
and	O
2.2	O
possible	O
with	O
software	O
update	O
on	O
OpenCL	B-Application
2.0	O
hardware	O
(	O
Broadwell+	O
)	O
with	O
future	O
software	O
updates	O
.	O
</s>
<s>
Support	O
for	O
Direct3D	B-Application
9	O
in	O
Mesa	O
is	O
only	O
implemented	O
for	O
Gallium3D-style	O
drivers	O
,	O
and	O
is	O
thus	O
only	O
available	O
with	O
the	O
newer	O
Gallium3D	O
Iris	O
driver	O
,	O
which	O
is	O
the	O
default	O
for	O
Broadwell+	O
since	O
Mesa	O
20.0	O
.	O
</s>
<s>
The	O
classic	O
Mesa	O
i965	O
driver	O
,	O
which	O
is	O
the	O
only	O
one	O
for	O
Haswell	B-Device
and	O
older	O
on	O
Linux	O
,	O
only	O
supports	O
core	B-Device
profile	O
for	O
OpenGL	B-Application
3.1	O
+	O
,	O
not	O
compatibility	O
profile	O
.	O
</s>
<s>
The	O
Iris	O
Gallium3D	O
driver	O
supports	O
compatibility	O
profile	O
for	O
OpenGL	B-Application
4.6	O
.	O
</s>
<s>
All	O
GVT	O
virtualization	O
methods	O
are	O
supported	O
since	O
the	O
Broadwell	B-General_Concept
processor	O
family	O
with	O
KVM	B-Application
and	O
Xen	B-Operating_System
.	O
</s>
<s>
Intel	O
developed	O
a	O
dedicated	O
SIP	O
core	B-Device
which	O
implements	O
multiple	O
video	O
decompression	O
and	O
compression	O
algorithms	O
branded	O
Intel	B-Algorithm
Quick	I-Algorithm
Sync	I-Algorithm
Video	I-Algorithm
.	O
</s>
<s>
+	O
Hardware-accelerated	O
video	O
compression	O
and	O
decompression	O
algorithms	O
present	O
in	O
Intel	B-Algorithm
Quick	I-Algorithm
Sync	I-Algorithm
Video	I-Algorithm
CPU'smicroarchitecture	O
Steps	O
video	O
compression	O
and	O
decompression	O
algorithms	O
H.265(HEVC )	O
H.264(MPEG-4 AVC )	O
H.262(MPEG-2 )	O
VC-1/WMV9	O
JPEG/MJPEG	O
VP8	B-Algorithm
VP9	B-Algorithm
AV1	B-Application
Westmere	B-Device
Decode	O
rowspan	O
=	O
2	O
rowspan	O
=	O
2	O
rowspan	O
=	O
2	O
rowspan	O
=	O
2	O
rowspan	O
=	O
2	O
Encode	O
Sandy	B-Device
Bridge	I-Device
Decode	O
Profiles	O
rowspan	O
=	O
6	O
ConstrainedBaseline	O
,	O
Main	O
,	O
High	O
,	O
StereoHighSimple	O
,	O
MainSimple	O
,	O
Main	O
,	O
Advanced	O
rowspan	O
=3	O
rowspan	O
=3	O
rowspan	O
=3	O
rowspan	O
=3	O
Levels	O
Max	O
.	O
</s>
<s>
resolution	O
Ivy	B-Device
Bridge	I-Device
Decode	O
Profiles	O
rowspan	O
=	O
6	O
ConstrainedBaseline	O
,	O
Main	O
,	O
High	O
,	O
StereoHighSimple	O
,	O
MainSimple	O
,	O
Main	O
,	O
AdvancedBaseline	O
rowspan	O
=3	O
rowspan	O
=3	O
rowspan	O
=3	O
Levels	O
Max	O
.	O
</s>
<s>
resolution	O
Haswell	B-Device
Decode	O
Profiles	O
Partial	O
8-bit	O
Main	O
,	O
High	O
,	O
SHP	O
,	O
MHPMainSimple	O
,	O
Main	O
,	O
AdvancedBaseline	O
rowspan	O
=3	O
rowspan	O
=3	O
rowspan	O
=3	O
Levels	O
4.1Main	O
,	O
HighHigh	O
,	O
3	O
Max	O
.	O
</s>
<s>
resolution1080/60p1080/60p16k	O
×16k	O
Broadwell	B-General_Concept
Decode	O
Profiles	O
Partial	O
8-bit	O
&	O
10-bit	O
MainSimple	O
,	O
Main	O
,	O
Advanced	O
0Partial	O
rowspan	O
=3	O
LevelsMain	O
,	O
HighHigh	O
,	O
3UnifiedMax	O
.	O
</s>
<s>
resolution1080/60p	O
Skylake	B-Architecture
Decode	O
Profiles	O
MainMain	O
,	O
High	O
,	O
SHP	O
,	O
MHPMainSimple	O
,	O
Main	O
,	O
AdvancedBaseline00	O
rowspan	O
=3	O
Levels5.25.2Main	O
,	O
HighHigh	O
,	O
3UnifiedUnifiedUnifiedMax	O
.	O
</s>
<s>
Intel	B-General_Concept
Pentium	I-General_Concept
&	O
Celeron	B-Device
family	O
GPU	B-Architecture
video	O
accelerationVED	O
(	O
Video	O
Encode	O
/	O
Decode	O
)	O
H.265/HEVC	B-Algorithm
H.264/MPEG	O
-4	O
AVC	O
H.262(MPEG-2 )	O
VC-1/WMV9	O
JPEG/MJPEG	O
VP8	B-Algorithm
VP9	B-Algorithm
Braswell	B-Device
DecodeProfile	O
Main	O
CBP	O
,	O
Main	O
,	O
High	O
Main	O
,	O
HighAdvanced	O
850	O
MP/s	O
4:2:0640	O
MP/s	O
4:2:2	O
420	O
MP/s	O
4:4:4	O
Level55.2High4Max	O
.	O
</s>
<s>
Intel	O
Atom	O
family	O
GPU	B-Architecture
video	O
accelerationVED	O
(	O
Video	O
Encode	O
/	O
Decode	O
)	O
H.265/HEVC	B-Algorithm
H.264/MPEG	O
-4	O
AVC	O
MPEG-4	B-Application
Visual	I-Application
H.263	B-Algorithm
H.262(MPEG-2 )	O
VC-1/WMV9	O
JPEG/MJPEG	O
VP8	B-Algorithm
VP9Bay	O
Trail-T	O
Decode	O
Profile	O
rowspan	O
=	O
"	O
6	O
"	O
Main	O
,	O
High	O
Main	O
0rowspan	O
=	O
"	O
6	O
"	O
Level5.1HighMax	O
.	O
</s>
<s>
Intel	O
releases	O
programming	O
manuals	O
for	O
most	O
of	O
Intel	B-Application
HD	I-Application
Graphics	I-Application
devices	O
via	O
its	O
Open	B-License
Source	I-License
Technology	I-License
Center	O
.	O
</s>
<s>
This	O
allows	O
various	O
open	B-License
source	I-License
enthusiasts	O
and	O
hackers	O
to	O
contribute	O
to	O
driver	O
development	O
,	O
and	O
port	O
drivers	O
to	O
various	O
operating	O
systems	O
,	O
without	O
the	O
need	O
for	O
reverse	O
engineering	O
.	O
</s>
