<s>
The	O
Intel	B-Device
Core	I-Device
microarchitecture	I-Device
(	O
provisionally	O
referred	O
to	O
as	O
Next	O
Generation	O
Micro-architecture	B-General_Concept
,	O
and	O
developed	O
as	O
Merom	B-Device
)	O
is	O
a	O
multi-core	B-Architecture
processor	I-Architecture
microarchitecture	B-General_Concept
launched	O
by	O
Intel	O
in	O
mid-2006	O
.	O
</s>
<s>
It	O
is	O
a	O
major	O
evolution	O
over	O
the	O
Yonah	B-Device
,	O
the	O
previous	O
iteration	O
of	O
the	O
P6	B-Device
microarchitecture	I-Device
series	I-Device
which	O
started	O
in	O
1995	O
with	O
Pentium	B-Device
Pro	I-Device
.	O
</s>
<s>
It	O
also	O
replaced	O
the	O
NetBurst	B-Device
microarchitecture	B-General_Concept
,	O
which	O
suffered	O
from	O
high	O
power	O
consumption	O
and	O
heat	O
intensity	O
due	O
to	O
an	O
inefficient	O
pipeline	B-General_Concept
designed	O
for	O
high	O
clock	O
rate	O
.	O
</s>
<s>
In	O
early	O
2004	O
the	O
new	O
version	O
of	O
NetBurst	B-Device
(	O
Prescott	O
)	O
needed	O
very	O
high	O
power	O
to	O
reach	O
the	O
clocks	O
it	O
needed	O
for	O
competitive	O
performance	O
,	O
making	O
it	O
unsuitable	O
for	O
the	O
shift	O
to	O
dual/multi	B-Architecture
-core	I-Architecture
CPUs	O
.	O
</s>
<s>
On	O
May	O
7	O
,	O
2004	O
Intel	O
confirmed	O
the	O
cancellation	O
of	O
the	O
next	O
NetBurst	B-Device
,	O
Tejas	B-Device
and	I-Device
Jayhawk	I-Device
.	O
</s>
<s>
Intel	O
had	O
been	O
developing	O
Merom	B-Device
,	O
the	O
64-bit	O
evolution	O
of	O
the	O
Pentium	B-Architecture
M	I-Architecture
,	O
since	O
2001	O
,	O
and	O
decided	O
to	O
expand	O
it	O
to	O
all	O
market	O
segments	O
,	O
replacing	O
NetBurst	B-Device
in	O
desktop	O
computers	O
and	O
servers	O
.	O
</s>
<s>
It	O
inherited	O
from	O
Pentium	B-Architecture
M	I-Architecture
the	O
choice	O
of	O
a	O
short	O
and	O
efficient	O
pipeline	B-General_Concept
,	O
delivering	O
superior	O
performance	O
despite	O
not	O
reaching	O
the	O
high	O
clocks	O
of	O
NetBurst	B-Device
.	O
</s>
<s>
The	O
first	O
processors	O
that	O
used	O
this	O
architecture	O
were	O
code-named	O
'	O
Merom	B-Device
 '	O
,	O
'	O
Conroe	O
 '	O
,	O
and	O
'	O
Woodcrest	O
 '	O
;	O
Merom	B-Device
is	O
for	O
mobile	O
computing	O
,	O
Conroe	O
is	O
for	O
desktop	B-General_Concept
systems	I-General_Concept
,	O
and	O
Woodcrest	O
is	O
for	O
servers	O
and	O
workstations	O
.	O
</s>
<s>
While	O
architecturally	O
identical	O
,	O
the	O
three	O
processor	B-General_Concept
lines	O
differ	O
in	O
the	O
socket	O
used	O
,	O
bus	O
speed	O
,	O
and	O
power	O
consumption	O
.	O
</s>
<s>
The	O
first	O
Core-based	O
desktop	O
and	O
mobile	O
processors	O
were	O
branded	O
Core	O
2	O
,	O
later	O
expanding	O
to	O
the	O
lower-end	O
Pentium	B-Device
Dual-Core	I-Device
,	O
Pentium	B-General_Concept
and	O
Celeron	B-Device
brands	O
;	O
while	O
server	O
and	O
workstation	O
Core-based	O
processors	O
were	O
branded	O
Xeon	B-Device
.	O
</s>
<s>
The	O
Core	B-Device
microarchitecture	I-Device
returned	O
to	O
lower	O
clock	O
rates	O
and	O
improved	O
the	O
use	O
of	O
both	O
available	O
clock	O
cycles	O
and	O
power	O
when	O
compared	O
with	O
the	O
preceding	O
NetBurst	B-Device
microarchitecture	B-General_Concept
of	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
and	O
D-branded	O
CPUs	O
.	O
</s>
<s>
The	O
Core	B-Device
microarchitecture	I-Device
provides	O
more	O
efficient	O
decoding	O
stages	O
,	O
execution	O
units	O
,	O
caches	O
,	O
and	O
buses	B-General_Concept
,	O
reducing	O
the	O
power	O
consumption	O
of	O
Core	O
2-branded	O
CPUs	O
while	O
increasing	O
their	O
processing	O
capacity	O
.	O
</s>
<s>
Intel	O
's	O
CPUs	O
have	O
varied	O
widely	O
in	O
power	O
consumption	O
according	O
to	O
clock	O
rate	O
,	O
architecture	O
,	O
and	O
semiconductor	O
process	O
,	O
shown	O
in	O
the	O
CPU	B-General_Concept
power	I-General_Concept
dissipation	I-General_Concept
tables	O
.	O
</s>
<s>
Like	O
the	O
last	O
NetBurst	B-Device
CPUs	O
,	O
Core	O
based	O
processors	O
feature	O
multiple	O
cores	O
and	O
hardware	O
virtualization	O
support	O
(	O
marketed	O
as	O
Intel	O
VT-x	O
)	O
,	O
and	O
Intel	O
64	O
and	O
SSSE3	B-General_Concept
.	O
</s>
<s>
However	O
,	O
Core-based	O
processors	O
do	O
not	O
have	O
the	O
hyper-threading	B-Operating_System
technology	I-Operating_System
as	O
in	O
Pentium	B-General_Concept
4	I-General_Concept
processors	O
.	O
</s>
<s>
This	O
is	O
because	O
the	O
Core	B-Device
microarchitecture	I-Device
is	O
based	O
on	O
the	O
P6	B-Device
microarchitecture	I-Device
used	O
by	O
Pentium	B-Device
Pro	I-Device
,	O
II	O
,	O
III	O
,	O
and	O
M	O
.	O
</s>
<s>
The	O
L1	O
cache	B-General_Concept
of	O
the	O
Core	B-Device
microarchitecture	I-Device
at	O
64KB	O
L1	O
cache/core	O
(	O
32KB	O
L1	O
Data	O
+	O
32KB	O
L1	O
Instruction	O
)	O
is	O
as	O
large	O
as	O
in	O
Pentium	B-Architecture
M	I-Architecture
,	O
up	O
from	O
32KB	O
on	O
Pentium	B-General_Concept
II/III	O
(	O
16KB	O
L1	O
Data	O
+	O
16KB	O
L1	O
Instruction	O
)	O
.	O
</s>
<s>
The	O
consumer	O
version	O
also	O
lacks	O
an	O
L3	O
cache	B-General_Concept
as	O
in	O
the	O
Gallatin	O
core	O
of	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
Extreme	I-General_Concept
Edition	I-General_Concept
,	O
though	O
it	O
is	O
exclusively	O
present	O
in	O
high-end	O
versions	O
of	O
Core-based	O
Xeons	B-Device
.	O
</s>
<s>
Both	O
an	O
L3	O
cache	B-General_Concept
and	O
hyper-threading	B-Operating_System
were	O
reintroduced	O
again	O
to	O
consumer	O
line	O
in	O
the	O
Nehalem	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
While	O
the	O
Core	B-Device
microarchitecture	I-Device
is	O
a	O
major	O
architectural	O
revision	O
,	O
it	O
is	O
based	O
in	O
part	O
on	O
the	O
Pentium	B-Architecture
M	I-Architecture
processor	B-General_Concept
family	O
designed	O
by	O
Intel	O
Israel	O
.	O
</s>
<s>
The	O
pipeline	B-General_Concept
of	O
Core/Penryn	O
is	O
14	O
stages	O
long	O
–	O
less	O
than	O
half	O
of	O
Prescott	O
's	O
.	O
</s>
<s>
Penryn	B-Device
's	O
successor	O
Nehalem	B-Device
has	O
a	O
two	O
cycles	O
higher	O
branch	O
misprediction	O
penalty	O
than	O
Core/Penryn	O
.	O
</s>
<s>
Core	O
can	O
ideally	O
sustain	O
up	O
to	O
4	O
instructions	O
per	O
cycle	O
(	O
IPC	O
)	O
execution	O
rate	O
,	O
compared	O
to	O
the	O
3	O
IPC	O
capability	O
of	O
P6	B-Device
,	O
Pentium	B-Architecture
M	I-Architecture
and	O
NetBurst	B-Device
microarchitectures	B-General_Concept
.	O
</s>
<s>
The	O
new	O
architecture	O
is	O
a	O
dual	B-Architecture
core	I-Architecture
design	O
with	O
a	O
shared	O
L2	O
cache	B-General_Concept
engineered	O
for	O
maximum	O
performance	O
per	O
watt	O
and	O
improved	O
scalability	O
.	O
</s>
<s>
One	O
new	O
technology	O
included	O
in	O
the	O
design	O
is	O
Macro-Ops	B-General_Concept
Fusion	O
,	O
which	O
combines	O
two	O
x86	B-Operating_System
instructions	O
into	O
a	O
single	O
micro-operation	B-General_Concept
.	O
</s>
<s>
For	O
example	O
,	O
a	O
common	O
code	O
sequence	O
like	O
a	O
compare	O
followed	O
by	O
a	O
conditional	O
jump	O
would	O
become	O
a	O
single	O
micro-op	B-General_Concept
.	O
</s>
<s>
Other	O
new	O
technologies	O
include	O
1	O
cycle	O
throughput	O
(	O
2	O
cycles	O
previously	O
)	O
of	O
all	O
128-bit	O
SSE	B-General_Concept
instructions	I-General_Concept
and	O
a	O
new	O
power	O
saving	O
design	O
.	O
</s>
<s>
All	O
components	O
will	O
run	O
at	O
minimum	O
speed	O
,	O
raising	O
speed	O
dynamically	O
as	O
needed	O
(	O
similar	O
to	O
AMD	O
's	O
Cool'n'Quiet	B-Device
power-saving	O
technology	O
,	O
and	O
Intel	O
's	O
own	O
SpeedStep	B-Device
technology	O
from	O
earlier	O
mobile	O
processors	O
)	O
.	O
</s>
<s>
For	O
most	O
Woodcrest	O
CPUs	O
,	O
the	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
runs	O
at	O
1333	O
MT/s	O
;	O
however	O
,	O
this	O
is	O
scaled	O
down	O
to	O
1066MT/s	O
for	O
lower	O
end	O
1.60	O
and	O
1.86GHz	O
variants	O
.	O
</s>
<s>
The	O
Merom	B-Device
mobile	O
variant	O
was	O
initially	O
targeted	O
to	O
run	O
at	O
an	O
FSB	O
of	O
667MT/s	O
while	O
the	O
second	O
wave	O
of	O
Meroms	B-Device
,	O
supporting	O
800MT/s	O
FSB	O
,	O
were	O
released	O
as	O
part	O
of	O
the	O
Santa	O
Rosa	O
platform	O
with	O
a	O
different	O
socket	O
in	O
May	O
2007	O
.	O
</s>
<s>
The	O
power	O
use	O
of	O
these	O
processors	O
is	O
very	O
low	O
:	O
average	O
energy	O
use	O
is	O
to	O
be	O
in	O
the	O
1	O
–	O
2	O
watt	O
range	O
in	O
ultra	O
low	O
voltage	O
variants	O
,	O
with	O
thermal	B-General_Concept
design	I-General_Concept
powers	I-General_Concept
(	O
TDPs	O
)	O
of	O
65	O
watts	O
for	O
Conroe	O
and	O
most	O
Woodcrests	O
,	O
80	O
watts	O
for	O
the	O
3.0GHz	O
Woodcrest	O
,	O
and	O
40	O
or	O
35	O
watts	O
for	O
the	O
low-voltage	O
Woodcrest	O
.	O
</s>
<s>
In	O
comparison	O
,	O
a	O
2.2GHz	O
AMD	B-General_Concept
Opteron	I-General_Concept
875HE	O
processor	B-General_Concept
consumes	O
55	O
watts	O
,	O
while	O
the	O
energy	O
efficient	O
Socket	O
AM2	O
line	O
fits	O
in	O
the	O
35	O
watt	O
thermal	O
envelope	O
(	O
specified	O
a	O
different	O
way	O
so	O
not	O
directly	O
comparable	O
)	O
.	O
</s>
<s>
Merom	B-Device
,	O
the	O
mobile	O
variant	O
,	O
is	O
listed	O
at	O
35	O
watts	O
TDP	O
for	O
standard	O
versions	O
and	O
5	O
watts	O
TDP	O
for	O
ultra	O
low	O
voltage	O
(	O
ULV	O
)	O
versions	O
.	O
</s>
<s>
The	O
processors	O
of	O
the	O
Core	B-Device
microarchitecture	I-Device
can	O
be	O
categorized	O
by	O
number	O
of	O
cores	O
,	O
cache	B-General_Concept
size	O
,	O
and	O
socket	O
;	O
each	O
combination	O
of	O
these	O
has	O
a	O
unique	O
code	O
name	O
and	O
product	O
code	O
that	O
is	O
used	O
across	O
several	O
brands	O
.	O
</s>
<s>
For	O
instance	O
,	O
code	O
name	O
"	O
Allendale	O
"	O
with	O
product	O
code	O
80557	O
has	O
two	O
cores	O
,	O
2	O
MB	O
L2	O
cache	B-General_Concept
and	O
uses	O
the	O
desktop	O
socket	B-Device
775	I-Device
,	O
but	O
has	O
been	O
marketed	O
as	O
Celeron	B-Device
,	O
Pentium	B-General_Concept
,	O
Core	O
2	O
,	O
and	O
Xeon	B-Device
,	O
each	O
with	O
different	O
sets	O
of	O
features	O
enabled	O
.	O
</s>
<s>
Most	O
of	O
the	O
mobile	O
and	O
desktop	O
processors	O
come	O
in	O
two	O
variants	O
that	O
differ	O
in	O
the	O
size	O
of	O
the	O
L2	O
cache	B-General_Concept
,	O
but	O
the	O
specific	O
amount	O
of	O
L2	O
cache	B-General_Concept
in	O
a	O
product	O
can	O
also	O
be	O
reduced	O
by	O
disabling	O
parts	O
at	O
production	O
time	O
.	O
</s>
<s>
Tigerton	O
dual-cores	B-Architecture
and	O
all	O
quad-core	B-Architecture
processors	I-Architecture
except	O
Dunnington	O
QC	O
are	O
multi-chip	B-Algorithm
modules	I-Algorithm
combining	O
two	O
dies	O
.	O
</s>
<s>
For	O
the	O
65nm	B-Algorithm
processors	O
,	O
the	O
same	O
product	O
code	O
can	O
be	O
shared	O
by	O
processors	O
with	O
different	O
dies	O
,	O
but	O
the	O
specific	O
information	O
about	O
which	O
one	O
is	O
used	O
can	O
be	O
derived	O
from	O
the	O
stepping	B-General_Concept
.	O
</s>
<s>
The	O
original	O
Core	O
2	O
processors	O
are	O
based	O
on	O
the	O
same	O
dies	O
that	O
can	O
be	O
identified	O
as	O
CPUID	B-Architecture
Family	O
6	O
Model	O
15	O
.	O
</s>
<s>
Depending	O
on	O
their	O
configuration	O
and	O
packaging	O
,	O
their	O
code	O
names	O
are	O
Conroe	O
(	O
LGA	B-Device
775	I-Device
,	O
4	O
MB	O
L2	O
cache	B-General_Concept
)	O
,	O
Allendale	O
(	O
LGA	B-Device
775	I-Device
,	O
2	O
MB	O
L2	O
cache	B-General_Concept
)	O
,	O
Merom	B-Device
(	O
Socket	B-Device
M	I-Device
,	O
4	O
MB	O
L2	O
cache	B-General_Concept
)	O
and	O
Kentsfield	B-Device
(	O
multi-chip	B-Algorithm
module	I-Algorithm
,	O
LGA	B-Device
775	I-Device
,	O
2x4MB	O
L2	O
cache	B-General_Concept
)	O
.	O
</s>
<s>
Merom	B-Device
and	O
Allendale	O
processors	O
with	O
limited	O
features	O
are	O
in	O
Pentium	B-Device
Dual	I-Device
Core	I-Device
and	O
Celeron	B-Device
processors	O
,	O
while	O
Conroe	O
,	O
Allendale	O
and	O
Kentsfield	B-Device
also	O
are	O
sold	O
as	O
Xeon	B-Device
processors	O
.	O
</s>
<s>
Additional	O
code	O
names	O
for	O
processors	O
based	O
on	O
this	O
model	O
are	O
Woodcrest	O
(	O
LGA	B-Device
771	I-Device
,	O
4	O
MB	O
L2	O
cache	B-General_Concept
)	O
,	O
Clovertown	B-Device
(	O
MCM	O
,	O
LGA	B-Device
771	I-Device
,	O
2×4MB	O
L2	O
cache	B-General_Concept
)	O
and	O
Tigerton	O
(	O
MCM	O
,	O
Socket	B-Device
604	I-Device
,	O
2×4MB	O
L2	O
cache	B-General_Concept
)	O
,	O
all	O
of	O
which	O
are	O
marketed	O
only	O
under	O
the	O
Xeon	B-Device
brand	O
.	O
</s>
<s>
The	O
Conroe-L	O
and	O
Merom-L	O
processors	O
are	O
based	O
around	O
the	O
same	O
core	O
as	O
Conroe	O
and	O
Merom	B-Device
,	O
but	O
only	O
contain	O
a	O
single	O
core	O
and	O
1	O
MB	O
of	O
L2	O
cache	B-General_Concept
,	O
significantly	O
reducing	O
production	O
cost	O
and	O
power	O
consumption	O
of	O
the	O
processor	B-General_Concept
at	O
the	O
expense	O
of	O
performance	O
compared	O
to	O
the	O
dual-core	B-Architecture
version	O
.	O
</s>
<s>
It	O
is	O
used	O
only	O
in	O
ultra-low	O
voltage	O
Core	O
2	O
Solo	O
U2xxx	O
and	O
in	O
Celeron	B-Device
processors	O
and	O
is	O
identified	O
as	O
CPUID	B-Architecture
family	O
6	O
model	O
22	O
.	O
</s>
<s>
In	O
Intel	O
's	O
Tick-Tock	B-Device
cycle	I-Device
,	O
the	O
2007/2008	O
"	O
Tick	O
"	O
was	O
the	O
shrink	O
of	O
the	O
Core	B-Device
microarchitecture	I-Device
to	O
45	B-Algorithm
nanometers	I-Algorithm
as	O
CPUID	B-Architecture
model	O
23	O
.	O
</s>
<s>
In	O
Core	O
2	O
processors	O
,	O
it	O
is	O
used	O
with	O
the	O
code	O
names	O
Penryn	B-Device
(	O
Socket	B-Device
P	I-Device
)	O
,	O
Wolfdale	B-Device
(	O
LGA	B-Device
775	I-Device
)	O
and	O
Yorkfield	B-Device
(	O
MCM	O
,	O
LGA	B-Device
775	I-Device
)	O
,	O
some	O
of	O
which	O
are	O
also	O
sold	O
as	O
Celeron	B-Device
,	O
Pentium	B-General_Concept
and	O
Xeon	B-Device
processors	O
.	O
</s>
<s>
In	O
the	O
Xeon	B-Device
brand	O
,	O
the	O
Wolfdale-DP	O
and	O
Harpertown	O
code	O
names	O
are	O
used	O
for	O
LGA	B-Device
771	I-Device
based	O
MCMs	O
with	O
two	O
or	O
four	O
active	O
Wolfdale	B-Device
cores	O
.	O
</s>
<s>
Architecturally	O
,	O
45nm	B-Algorithm
Core	O
2	O
processors	O
feature	O
SSE4.1	B-General_Concept
and	O
new	O
divide/shuffle	O
engine	O
.	O
</s>
<s>
The	O
chips	O
come	O
in	O
two	O
sizes	O
,	O
with	O
6	O
MB	O
and	O
3	O
MB	O
L2	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
smaller	O
version	O
is	O
commonly	O
called	O
Penryn-3M	O
and	O
Wolfdale-3M	O
and	O
Yorkfield-6M	O
,	O
respectively	O
.	O
</s>
<s>
The	O
single-core	O
version	O
of	O
Penryn	B-Device
,	O
listed	O
as	O
Penryn-L	O
here	O
,	O
is	O
not	O
a	O
separate	O
model	O
like	O
Merom-L	O
but	O
a	O
version	O
of	O
the	O
Penryn-3M	O
model	O
with	O
only	O
one	O
active	O
core	O
.	O
</s>
<s>
The	O
Xeon	B-Device
"	O
Dunnington	O
"	O
processor	B-General_Concept
(	O
CPUID	B-Architecture
Family	O
6	O
,	O
model	O
29	O
)	O
is	O
closely	O
related	O
to	O
Wolfdale	B-Device
but	O
comes	O
with	O
six	O
cores	O
and	O
an	O
on-chip	O
L3	O
cache	B-General_Concept
and	O
is	O
designed	O
for	O
servers	O
with	O
Socket	B-Device
604	I-Device
,	O
so	O
it	O
is	O
marketed	O
only	O
as	O
Xeon	B-Device
,	O
not	O
as	O
Core	O
2	O
.	O
</s>
<s>
The	O
Core	B-Device
microarchitecture	I-Device
uses	O
several	O
stepping	B-General_Concept
levels	I-General_Concept
(	O
steppings	B-General_Concept
)	O
,	O
which	O
unlike	O
prior	O
microarchitectures	B-General_Concept
,	O
represent	O
incremental	O
improvements	O
,	O
and	O
different	O
sets	O
of	O
features	O
like	O
cache	B-General_Concept
size	O
and	O
low	O
power	O
modes	O
.	O
</s>
<s>
Most	O
of	O
these	O
steppings	B-General_Concept
are	O
used	O
across	O
brands	O
,	O
typically	O
by	O
disabling	O
some	O
features	O
and	O
limiting	O
clock	O
frequencies	O
on	O
low-end	O
chips	O
.	O
</s>
<s>
Steppings	B-General_Concept
with	O
a	O
reduced	O
cache	B-General_Concept
size	O
use	O
a	O
separate	O
naming	O
scheme	O
,	O
which	O
means	O
that	O
the	O
releases	O
are	O
no	O
longer	O
in	O
alphabetic	O
order	O
.	O
</s>
<s>
Added	O
steppings	B-General_Concept
have	O
been	O
used	O
in	O
internal	O
and	O
engineering	O
samples	O
,	O
but	O
are	O
unlisted	O
in	O
the	O
tables	O
.	O
</s>
<s>
Many	O
of	O
the	O
high-end	O
Core	O
2	O
and	O
Xeon	B-Device
processors	O
use	O
Multi-chip	B-Algorithm
modules	I-Algorithm
of	O
two	O
chips	O
in	O
order	O
to	O
get	O
larger	O
cache	B-General_Concept
sizes	O
or	O
more	O
than	O
two	O
cores	O
.	O
</s>
<s>
Mobile	O
(	O
Merom	B-Device
)	O
Desktop	O
(	O
Conroe	O
)	O
Desktop	O
(	O
Kentsfield	B-Device
)	O
Server	O
(	O
Woodcrest	O
,	O
Clovertown	B-Device
,	O
Tigerton	O
)	O
Stepping	B-General_Concept
Released	O
Area	O
CPUID	B-Architecture
L2	O
cache	B-General_Concept
Max	O
.	O
</s>
<s>
Early	O
ES/QS	O
steppings	B-General_Concept
are	O
:	O
B0	O
(	O
CPUID	B-Architecture
6F4h	O
)	O
,	O
B1	O
(	O
6F5h	O
)	O
and	O
E0	O
(	O
6F9h	O
)	O
.	O
</s>
<s>
Steppings	B-General_Concept
B2/B3	O
,	O
E1	O
,	O
and	O
G0	O
of	O
model	O
15	O
(	O
cpuid	B-Architecture
06fx	O
)	O
processors	O
are	O
evolutionary	O
steps	O
of	O
the	O
standard	O
Merom/Conroe	O
die	O
with	O
4MB	O
L2	O
cache	B-General_Concept
,	O
with	O
the	O
short-lived	O
E1	O
stepping	B-General_Concept
only	O
being	O
used	O
in	O
mobile	O
processors	O
.	O
</s>
<s>
Stepping	B-General_Concept
L2	O
and	O
M0	O
are	O
the	O
Allendale	O
chips	O
with	O
just	O
2MB	O
L2	O
cache	B-General_Concept
,	O
reducing	O
production	O
cost	O
and	O
power	O
consumption	O
for	O
low-end	O
processors	O
.	O
</s>
<s>
The	O
G0	O
and	O
M0	O
steppings	B-General_Concept
improve	O
idle	O
power	O
consumption	O
in	O
C1E	O
state	O
and	O
add	O
the	O
C2E	O
state	O
in	O
desktop	O
processors	O
.	O
</s>
<s>
In	O
mobile	O
processors	O
,	O
all	O
of	O
which	O
support	O
C1	O
through	O
C4	O
idle	O
states	O
,	O
steppings	B-General_Concept
E1	O
,	O
G0	O
,	O
and	O
M0	O
add	O
support	O
for	O
the	O
Mobile	O
Intel	O
965	O
Express	O
(	O
Santa	O
Rosa	O
)	O
platform	O
with	O
Socket	B-Device
P	I-Device
,	O
while	O
the	O
earlier	O
B2	O
and	O
L2	O
steppings	B-General_Concept
only	O
appear	O
for	O
the	O
Socket	B-Device
M	I-Device
based	O
Mobile	O
Intel	O
945	O
Express	O
(	O
Napa	O
refresh	O
)	O
platform	O
.	O
</s>
<s>
The	O
model	O
22	O
stepping	B-General_Concept
A1	O
(	O
cpuid	B-Architecture
10661h	O
)	O
marks	O
a	O
significant	O
design	O
change	O
,	O
with	O
just	O
a	O
single	O
core	O
and	O
1MB	O
L2	O
cache	B-General_Concept
further	O
reducing	O
the	O
power	O
consumption	O
and	O
manufacturing	O
cost	O
for	O
the	O
low-end	O
.	O
</s>
<s>
Like	O
the	O
earlier	O
steppings	B-General_Concept
,	O
A1	O
is	O
not	O
used	O
with	O
the	O
Mobile	O
Intel	O
965	O
Express	O
platform	O
.	O
</s>
<s>
Steppings	B-General_Concept
G0	O
,	O
M0	O
and	O
A1	O
mostly	O
replaced	O
all	O
older	O
steppings	B-General_Concept
in	O
2008	O
.	O
</s>
<s>
In	O
2009	O
,	O
a	O
new	O
stepping	B-General_Concept
G2	O
was	O
introduced	O
to	O
replace	O
the	O
original	O
stepping	B-General_Concept
B2	O
.	O
</s>
<s>
Mobile	O
(	O
Penryn	B-Device
)	O
Desktop	O
(	O
Wolfdale	B-Device
)	O
Desktop	O
(	O
Yorkfield	B-Device
)	O
Server	O
(	O
Wolfdale-DP	O
,	O
Harpertown	O
,	O
Dunnington	O
)	O
Stepping	B-General_Concept
Released	O
Area	O
CPUID	B-Architecture
L2	O
cache	B-General_Concept
Max	O
.	O
</s>
<s>
In	O
the	O
model	O
23	O
(	O
cpuid	B-Architecture
01067xh	O
)	O
,	O
Intel	O
started	O
marketing	O
stepping	B-General_Concept
with	O
full	O
(	O
6MB	O
)	O
and	O
reduced	O
(	O
3MB	O
)	O
L2	O
cache	B-General_Concept
at	O
the	O
same	O
time	O
,	O
and	O
giving	O
them	O
identical	O
cpuid	B-Architecture
values	O
.	O
</s>
<s>
All	O
steppings	B-General_Concept
have	O
the	O
new	O
SSE4.1	B-General_Concept
instructions	O
.	O
</s>
<s>
Stepping	B-General_Concept
C1/M1	O
was	O
a	O
bug	O
fix	O
version	O
of	O
C0/M0	O
specifically	O
for	O
quad	B-Architecture
core	I-Architecture
processors	O
and	O
only	O
used	O
in	O
those	O
.	O
</s>
<s>
Stepping	B-General_Concept
E0/R0	O
adds	O
two	O
new	O
instructions	O
(	O
XSAVE/XRSTOR	O
)	O
and	O
replaces	O
all	O
earlier	O
steppings	B-General_Concept
.	O
</s>
<s>
In	O
mobile	O
processors	O
,	O
stepping	B-General_Concept
C0/M0	O
is	O
only	O
used	O
in	O
the	O
Intel	O
Mobile	O
965	O
Express	O
(	O
Santa	O
Rosa	O
refresh	O
)	O
platform	O
,	O
whereas	O
stepping	B-General_Concept
E0/R0	O
supports	O
the	O
later	O
Intel	O
Mobile	O
4	O
Express	O
(	O
Montevina	O
)	O
platform	O
.	O
</s>
<s>
Model	O
30	O
stepping	B-General_Concept
A1	O
(	O
cpuid	B-Architecture
106d1h	O
)	O
adds	O
an	O
L3	O
cache	B-General_Concept
and	O
six	O
instead	O
of	O
the	O
usual	O
two	O
cores	O
,	O
which	O
leads	O
to	O
an	O
unusually	O
large	O
die	O
size	O
of	O
503mm²	O
.	O
</s>
<s>
As	O
of	O
February	O
2008	O
,	O
it	O
has	O
only	O
found	O
its	O
way	O
into	O
the	O
very	O
high-end	O
Xeon	B-Device
7400	O
series	O
(	O
Dunnington	O
)	O
.	O
</s>
<s>
Conroe	O
,	O
Conroe	O
XE	O
and	O
Allendale	O
all	O
use	O
Socket	O
LGA	B-Device
775	I-Device
;	O
however	O
,	O
not	O
every	O
motherboard	B-Device
is	O
compatible	O
with	O
these	O
processors	O
.	O
</s>
<s>
Supporting	O
chipsets	B-Device
are	O
:	O
</s>
<s>
NVIDIA	O
:	O
nForce4	B-Device
Ultra/SLI	O
X16	O
for	O
Intel	O
,	O
nForce	B-Device
570/590	I-Device
SLI	I-Device
for	O
Intel	O
,	O
nForce	B-Device
650i	I-Device
Ultra/650i	I-Device
SLI/680i	I-Device
LT	I-Device
SLI/680i	I-Device
SLI	I-Device
and	O
nForce	B-Device
750i	I-Device
SLI/780i	I-Device
SLI/790i	I-Device
SLI/790i	I-Device
Ultra	I-Device
SLI	I-Device
.	O
</s>
<s>
The	O
Yorkfield	B-Device
XE	O
model	O
QX9770	O
(	O
45nm	B-Algorithm
with	O
1600	O
MT/s	O
FSB	O
)	O
has	O
limited	O
chipset	B-Device
compatibility	O
-	O
with	O
only	O
X38	O
,	O
P35	O
(	O
With	O
Overclocking	B-Application
)	O
and	O
some	O
high-performance	O
X48	O
and	O
P45	O
motherboards	B-Device
being	O
compatible	O
.	O
</s>
<s>
BIOS	B-Operating_System
updates	O
were	O
gradually	O
being	O
released	O
to	O
provide	O
support	O
for	O
the	O
Penryn	B-Device
technology	O
,	O
and	O
the	O
QX9775	O
is	O
only	O
compatible	O
with	O
the	O
Intel	O
D5400XS	O
motherboard	B-Device
.	O
</s>
<s>
The	O
Wolfdale-3M	O
model	O
E7200	O
also	O
has	O
limited	O
compatibility	O
(	O
at	O
least	O
the	O
Xpress	B-Device
200	I-Device
chipset	B-Device
is	O
incompatible	O
)	O
.	O
</s>
<s>
Although	O
a	O
motherboard	B-Device
may	O
have	O
the	O
required	O
chipset	B-Device
to	O
support	O
Conroe	O
,	O
some	O
motherboards	B-Device
based	O
on	O
the	O
above-mentioned	O
chipsets	B-Device
do	O
not	O
support	O
Conroe	O
.	O
</s>
<s>
This	O
requirement	O
is	O
a	O
result	O
of	O
Conroe	O
's	O
significantly	O
lower	O
power	O
consumption	O
,	O
compared	O
to	O
the	O
Pentium	O
4/D	O
CPUs	O
it	O
replaced	O
.	O
</s>
<s>
A	O
motherboard	B-Device
that	O
has	O
both	O
a	O
supporting	O
chipset	B-Device
and	O
VRD	O
11	O
supports	O
Conroe	O
processors	O
,	O
but	O
even	O
then	O
some	O
boards	O
will	O
need	O
an	O
updated	O
BIOS	B-Operating_System
to	O
recognize	O
Conroe	O
's	O
FID	O
(	O
Frequency	O
ID	O
)	O
and	O
VID	O
(	O
Voltage	O
ID	O
)	O
.	O
</s>
<s>
Unlike	O
the	O
prior	O
Pentium	B-General_Concept
4	I-General_Concept
and	O
Pentium	B-Device
D	I-Device
design	O
,	O
the	O
Core	O
2	O
technology	O
sees	O
a	O
greater	O
benefit	O
from	O
memory	O
running	O
synchronously	O
with	O
the	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
.	O
</s>
<s>
The	O
used	O
by	O
all	O
NetBurst	B-Device
processors	O
and	O
current	O
and	O
medium-term	O
(	O
pre-QuickPath	O
)	O
Core	O
2	O
processors	O
provide	O
a	O
64-bit	O
data	O
path	O
.	O
</s>
<s>
Current	O
chipsets	B-Device
provide	O
for	O
a	O
couple	O
of	O
either	O
DDR2	O
or	O
DDR3	O
channels	O
.	O
</s>
<s>
On	O
jobs	O
requiring	O
large	O
amounts	O
of	O
memory	O
access	O
,	O
the	O
quad-core	B-Architecture
Core	O
2	O
processors	O
can	O
benefit	O
significantly	O
from	O
using	O
PC2-8500	O
memory	O
,	O
which	O
runs	O
at	O
the	O
same	O
speed	O
as	O
the	O
CPU	O
's	O
FSB	O
;	O
this	O
is	O
not	O
an	O
officially	O
supported	O
configuration	O
,	O
but	O
several	O
motherboards	B-Device
support	O
it	O
.	O
</s>
<s>
The	O
Core	O
2	O
processor	B-General_Concept
does	O
not	O
require	O
the	O
use	O
of	O
DDR2	O
.	O
</s>
<s>
While	O
the	O
Intel	O
975X	O
and	O
P965	O
chipsets	B-Device
require	O
this	O
memory	O
,	O
some	O
motherboards	B-Device
and	O
chipsets	B-Device
support	O
both	O
Core	O
2	O
processors	O
and	O
DDR	O
memory	O
.	O
</s>
<s>
The	O
Core	O
2	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
in	O
X6800	O
,	O
E6000	O
and	O
E4000	O
processors	O
does	O
not	O
operate	O
to	O
prior	O
specifications	O
implemented	O
in	O
prior	O
generations	O
of	O
x86	B-Operating_System
hardware	O
.	O
</s>
<s>
This	O
may	O
cause	O
problems	O
,	O
many	O
of	O
them	O
serious	O
security	O
and	O
stability	O
issues	O
,	O
with	O
extant	O
operating	B-General_Concept
system	I-General_Concept
software	O
.	O
</s>
<s>
Intel	O
's	O
documentation	O
states	O
that	O
their	O
programming	O
manuals	O
will	O
be	O
updated	O
"	O
in	O
the	O
coming	O
months	O
"	O
with	O
information	O
on	O
recommended	O
methods	O
of	O
managing	O
the	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
for	O
Core	O
2	O
to	O
avoid	O
issues	O
,	O
and	O
admits	O
that	O
,	O
"	O
in	O
rare	O
instances	O
,	O
improper	O
TLB	O
invalidation	O
may	O
result	O
in	O
unpredictable	O
system	O
behavior	O
,	O
such	O
as	O
hangs	O
or	O
incorrect	O
data.	O
"	O
</s>
<s>
Non-execute	B-General_Concept
bit	O
is	O
shared	O
across	O
the	O
cores	O
.	O
</s>
<s>
39	O
,	O
43	O
,	O
79	O
,	O
which	O
can	O
cause	O
unpredictable	O
behavior	O
or	O
system	O
hang	O
,	O
have	O
been	O
fixed	O
in	O
recent	O
steppings	B-General_Concept
.	O
</s>
<s>
Among	O
those	O
who	O
have	O
stated	O
the	O
errata	O
to	O
be	O
particularly	O
serious	O
are	O
OpenBSD	B-Operating_System
's	O
Theo	O
de	O
Raadt	O
and	O
DragonFly	B-Application
BSD	I-Application
's	O
Matthew	O
Dillon	O
.	O
</s>
<s>
Microsoft	O
has	O
issued	O
update	O
KB936357	O
to	O
address	O
the	O
errata	O
by	O
microcode	B-Device
update	O
,	O
with	O
no	O
performance	O
penalty	O
.	O
</s>
<s>
BIOS	B-Operating_System
updates	O
are	O
also	O
available	O
to	O
fix	O
the	O
issue	O
.	O
</s>
