<s>
The	O
Intel	B-Device
8255	I-Device
(	O
or	O
i8255	B-Device
)	O
Programmable	O
Peripheral	O
Interface	B-Application
(	O
PPI	O
)	O
chip	O
was	O
developed	O
and	O
manufactured	O
by	O
Intel	O
in	O
the	O
first	O
half	O
of	O
the	O
1970s	O
for	O
the	O
Intel	B-General_Concept
8080	I-General_Concept
microprocessor	B-Architecture
.	O
</s>
<s>
The	O
8255	B-Device
provides	O
24	O
parallel	O
input/output	B-General_Concept
lines	O
with	O
a	O
variety	O
of	O
programmable	O
operating	O
modes	O
.	O
</s>
<s>
The	O
8255	B-Device
is	O
a	O
member	O
of	O
the	O
MCS-85	B-General_Concept
Family	O
of	O
chips	O
,	O
designed	O
by	O
Intel	O
for	O
use	O
with	O
their	O
8085	B-General_Concept
and	O
8086	B-General_Concept
microprocessors	I-General_Concept
and	O
their	O
descendants	O
.	O
</s>
<s>
It	O
was	O
first	O
available	O
in	O
a	O
40-pin	O
DIP	B-Algorithm
and	O
later	O
a	O
44-pin	O
PLCC	B-Algorithm
packages	O
.	O
</s>
<s>
The	O
82C55	O
is	O
a	O
CMOS	B-Device
version	O
for	O
higher	O
speed	O
and	O
lower	O
current	O
consumption	O
.	O
</s>
<s>
The	O
functionality	O
of	O
the	O
8255	B-Device
is	O
now	O
mostly	O
embedded	O
in	O
larger	O
VLSI	O
processing	O
chips	O
as	O
a	O
sub-function	O
.	O
</s>
<s>
A	O
CMOS	B-Device
version	O
of	O
the	O
8255	B-Device
is	O
still	O
being	O
made	O
by	O
Renesas	O
but	O
mostly	O
used	O
to	O
expand	O
the	O
I/O	B-General_Concept
of	O
microcontrollers	B-Architecture
.	O
</s>
<s>
The	O
8255	B-Device
has	O
a	O
similar	O
function	O
to	O
the	O
Motorola	B-General_Concept
6820	I-General_Concept
PIA	I-General_Concept
(	O
Peripheral	B-General_Concept
Interface	I-General_Concept
Adapter	I-General_Concept
)	O
from	O
the	O
Motorola	B-Device
6800	I-Device
family	O
,	O
also	O
originally	O
packaged	O
as	O
40-pin	O
DIL	O
.	O
</s>
<s>
The	O
8255	B-Device
provides	O
24	O
I/O	B-General_Concept
pins	O
with	O
four	O
programmable	O
direction	O
bits	O
:	O
one	O
for	O
Port	O
A( 	O
7:0	O
)	O
(	O
i.e.	O
,	O
all	O
pins	O
in	O
the	O
port	O
)	O
,	O
one	O
for	O
Port	O
B( 	O
7:0	O
)	O
,	O
one	O
for	O
Port	O
C( 	O
3:0	O
)	O
and	O
one	O
for	O
Port	O
C( 	O
7:4	O
)	O
.	O
</s>
<s>
By	O
contrast	O
,	O
the	O
Motorola	O
and	O
MOS	O
chips	O
provide	O
only	O
16	O
I/O	B-General_Concept
pins	O
plus	O
4	O
control	O
pins	O
,	O
but	O
the	O
Motorola/MOS	O
chips	O
allow	O
the	O
direction	O
(	O
input	O
or	O
output	O
)	O
of	O
all	O
I/O	B-General_Concept
pins	O
to	O
be	O
individually	O
programmed	O
.	O
</s>
<s>
Other	O
comparable	O
microprocessor	B-Architecture
I/O	B-General_Concept
chips	O
are	O
the	O
2655	O
Programmable	O
Peripheral	O
Interface	B-Application
from	O
the	O
Signetics	B-General_Concept
2650	I-General_Concept
family	O
,	O
the	O
Z80	O
PIO	O
,	O
the	O
Western	O
Design	O
Center	O
WDC	B-Application
65C21	I-Application
(	O
equivalent	O
to	O
the	O
Motorola	O
6820/6821	O
)	O
,	O
and	O
the	O
MOS	B-Device
Technology	I-Device
6522	I-Device
VIA	O
and	O
6526	B-Device
CIA	I-Device
which	O
had	O
considerable	O
additional	O
functionality	O
such	O
as	O
timers	O
and	O
shift	O
registers	O
.	O
</s>
<s>
The	O
available	O
82C55A	O
CMOS	B-Device
version	O
was	O
outsourced	O
to	O
Oki	O
Electronic	O
Industry	O
Co.	O
,	O
Ltd	O
.	O
</s>
<s>
The	O
available	O
package	O
from	O
Intel	O
branded	O
82C55	O
in	O
44-pin	O
PLCC	B-Algorithm
of	O
sampling	O
at	O
fourth	O
quarter	O
of	O
1985	O
.	O
</s>
<s>
The	O
8255	B-Device
was	O
widely	O
used	O
in	O
many	O
microcomputer/microcontroller	O
systems	O
and	O
home	O
computers	O
such	O
as	O
the	O
SV-328	B-Device
and	O
all	O
MSX	B-Operating_System
models	O
.	O
</s>
<s>
The	O
8255	B-Device
was	O
used	O
in	O
the	O
original	O
IBM-PC	B-Device
,	O
PC/XT	O
,	O
PC/jr	O
and	O
clones	O
,	O
along	O
with	O
numerous	O
homebuilt	B-Device
computers	I-Device
such	O
as	O
the	O
N8VEM	B-Device
.	O
</s>
<s>
The	O
8255	B-Device
gives	O
a	O
CPU	O
or	O
digital	O
system	O
access	O
to	O
programmable	O
parallel	O
I/O	B-General_Concept
.	O
</s>
<s>
The	O
8255	B-Device
has	O
24	O
input/output	B-General_Concept
pins	O
.	O
</s>
<s>
Port	O
A	O
and	O
port	O
B	O
can	O
be	O
used	O
as	O
8-bit	O
input/output	B-General_Concept
ports	O
.	O
</s>
<s>
Port	O
C	O
can	O
be	O
used	O
as	O
an	O
8-bit	O
input/output	B-General_Concept
port	O
or	O
as	O
two	O
4-bit	O
input/output	B-General_Concept
ports	O
or	O
to	O
produce	O
handshake	O
signals	O
for	O
ports	O
A	O
and	O
B	O
.	O
</s>
<s>
The	O
control	O
signal	O
chip	O
select	O
CS	O
(	O
pin	O
6	O
)	O
is	O
used	O
to	O
enable	O
the	O
8255	B-Device
chip	O
.	O
</s>
<s>
It	O
is	O
an	O
active-low	O
signal	O
,	O
i.e.	O
,	O
when	O
CS	O
=	O
0	O
,	O
the	O
8255	B-Device
is	O
enabled	O
.	O
</s>
<s>
The	O
RESET	O
input	O
(	O
pin	O
35	O
)	O
is	O
connected	O
to	O
the	O
RESET	O
line	O
of	O
system	O
like	O
8085	B-General_Concept
,	O
8086	B-General_Concept
,	O
etc.	O
,	O
so	O
that	O
when	O
the	O
system	O
is	O
reset	O
,	O
all	O
the	O
ports	O
are	O
initialized	O
as	O
input	O
lines	O
.	O
</s>
<s>
This	O
is	O
done	O
to	O
prevent	O
8255	B-Device
and/or	O
any	O
peripheral	O
connected	O
to	O
it	O
from	O
being	O
destroyed	O
due	O
to	O
mismatch	O
of	O
port	O
direction	O
settings	O
.	O
</s>
<s>
As	O
an	O
example	O
,	O
consider	O
an	O
input	O
device	O
connected	O
to	O
8255	B-Device
at	O
port	O
A	O
.	O
</s>
<s>
If	O
from	O
the	O
previous	O
operation	O
,	O
port	O
A	O
is	O
initialized	O
as	O
an	O
output	O
port	O
and	O
if	O
8255	B-Device
is	O
not	O
reset	O
before	O
using	O
the	O
current	O
configuration	O
,	O
then	O
there	O
is	O
a	O
possibility	O
of	O
damage	O
of	O
either	O
the	O
input	O
device	O
connected	O
or	O
8255	B-Device
or	O
both	O
,	O
since	O
both	O
8255	B-Device
and	O
the	O
device	O
connected	O
will	O
be	O
sending	O
out	O
data	O
.	O
</s>
<s>
The	O
control	O
register	O
(	O
or	O
the	O
control	O
logic	O
,	O
or	O
the	O
command	O
word	O
register	O
)	O
is	O
an	O
8-bit	O
register	O
used	O
to	O
select	O
the	O
modes	O
of	O
operation	O
and	O
input/output	B-General_Concept
designation	O
of	O
the	O
ports	O
.	O
</s>
<s>
There	O
are	O
two	O
basic	O
operational	O
modes	O
of	O
8255	B-Device
:	O
</s>
<s>
Input/Output	B-General_Concept
mode	O
(	O
I/O	B-General_Concept
mode	O
)	O
.	O
</s>
<s>
When	O
D7	O
=	O
1	O
,	O
8255	B-Device
operates	O
in	O
I/O	B-General_Concept
mode	O
,	O
and	O
when	O
D7	O
=	O
0	O
,	O
it	O
operates	O
in	O
the	O
BSR	O
mode	O
.	O
</s>
<s>
BSR	O
mode	O
and	O
I/O	B-General_Concept
mode	O
are	O
independent	O
and	O
selection	O
of	O
BSR	O
mode	O
does	O
not	O
affect	O
the	O
operation	O
of	O
other	O
ports	O
in	O
I/O	B-General_Concept
mode	O
.	O
</s>
<s>
There	O
are	O
three	O
I/O	B-General_Concept
modes	O
:	O
</s>
<s>
As	O
it	O
is	O
I/O	B-General_Concept
mode	O
,	O
D7	O
=	O
1	O
.	O
</s>
<s>
Since	O
it	O
is	O
an	O
I/O	B-General_Concept
mode	O
,	O
D7	O
=	O
1	O
.	O
</s>
<s>
In	O
this	O
mode	O
,	O
the	O
ports	O
can	O
be	O
used	O
for	O
simple	O
I/O	B-General_Concept
operations	I-General_Concept
without	O
handshaking	O
signals	O
.	O
</s>
<s>
Port	O
A	O
,	O
port	O
B	O
provide	O
simple	O
I/O	B-General_Concept
operation	I-General_Concept
.	O
</s>
<s>
The	O
input/output	B-General_Concept
features	O
in	O
mode	O
0	O
are	O
as	O
follows	O
:	O
</s>
<s>
With	O
4	O
ports	O
,	O
16	O
different	O
combinations	O
of	O
I/O	B-General_Concept
are	O
possible	O
.	O
</s>
<s>
The	O
8255	B-Device
's	O
outputs	O
are	O
latched	O
to	O
hold	O
the	O
last	O
data	O
written	O
to	O
them	O
.	O
</s>
<s>
In	O
the	O
input	O
mode	O
,	O
the	O
8255	B-Device
gets	O
data	O
from	O
the	O
external	O
peripheral	O
ports	O
and	O
the	O
CPU	O
reads	O
the	O
received	O
data	O
via	O
its	O
data	O
bus	O
.	O
</s>
<s>
The	O
CPU	O
first	O
selects	O
the	O
8255	B-Device
chip	O
by	O
making	O
CS	O
low	O
.	O
</s>
<s>
In	O
the	O
output	O
mode	O
,	O
the	O
CPU	O
sends	O
data	O
to	O
8255	B-Device
via	O
system	O
data	O
bus	O
and	O
then	O
the	O
external	O
peripheral	O
ports	O
receive	O
this	O
data	O
via	O
8255	B-Device
port	O
.	O
</s>
<s>
CPU	O
first	O
selects	O
the	O
8255	B-Device
chip	O
by	O
making	O
CS	O
low	O
.	O
</s>
<s>
Pins	O
PC6	O
and	O
PC7	O
are	O
available	O
for	O
use	O
as	O
input/output	B-General_Concept
lines	O
.	O
</s>
<s>
port	O
A	O
and	O
B	O
can	O
be	O
used	O
as	O
8-bit	O
i/o	B-General_Concept
ports	O
.	O
</s>
<s>
Each	O
port	O
uses	O
three	O
lines	O
of	O
port	O
c	O
as	O
handshake	O
signal	O
and	O
remaining	O
two	O
signals	O
can	O
be	O
used	O
as	O
i/o	B-General_Concept
ports	O
.	O
</s>
<s>
Input	B-General_Concept
and	I-General_Concept
Output	I-General_Concept
data	O
are	O
latched	O
.	O
</s>
<s>
STB	O
(	O
Strobed	O
Input	O
)	O
-	O
The	O
strobe	O
input	O
loads	O
data	O
into	O
the	O
port	O
latch	O
,	O
which	O
holds	O
the	O
information	O
until	O
it	O
is	O
input	O
to	O
the	O
microprocessor	B-Architecture
via	O
the	O
IN	O
instruction	O
.	O
</s>
<s>
The	O
INTR	O
pin	O
becomes	O
a	O
logic	O
1	O
when	O
the	O
STB	O
input	O
returns	O
to	O
a	O
logic	O
1	O
,	O
and	O
is	O
cleared	O
when	O
the	O
data	O
are	O
input	O
from	O
the	O
port	O
by	O
the	O
microprocessor	B-Architecture
.	O
</s>
<s>
INTR	O
(	O
Interrupt	O
request	O
)	O
-	O
It	O
is	O
a	O
signal	O
that	O
often	O
interrupts	O
the	O
microprocessor	B-Architecture
when	O
the	O
external	O
device	O
receives	O
the	O
data	O
via	O
the	O
signal	O
.	O
</s>
<s>
The	O
remaining	O
pins	O
of	O
port	O
C	O
(	O
PC0	O
-	O
PC2	O
)	O
can	O
be	O
used	O
as	O
input/output	B-General_Concept
lines	O
if	O
group	O
B	O
is	O
initialized	O
in	O
mode	O
0	O
or	O
as	O
handshaking	O
for	O
port	O
B	O
if	O
group	O
B	O
is	O
initialized	O
in	O
mode	O
1	O
.	O
</s>
<s>
In	O
this	O
mode	O
,	O
the	O
8255	B-Device
may	O
be	O
used	O
to	O
extend	O
the	O
system	O
bus	O
to	O
a	O
slave	O
microprocessor	B-Architecture
or	O
to	O
transfer	O
data	O
bytes	O
to	O
and	O
from	O
a	O
floppy	B-Device
disk	I-Device
controller	O
.	O
</s>
