<s>
Intel	B-Device
8237	I-Device
is	O
a	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	O
)	O
controller	O
,	O
a	O
part	O
of	O
the	O
MCS	O
85	O
microprocessor	O
family	O
.	O
</s>
<s>
The	O
8237	B-Device
is	O
a	O
four-channel	O
device	O
that	O
can	O
be	O
expanded	O
to	O
include	O
any	O
number	O
of	O
DMA	O
channel	O
inputs	O
.	O
</s>
<s>
The	O
8237	B-Device
is	O
capable	O
of	O
DMA	O
transfers	O
at	O
rates	O
of	O
up	O
to	O
per	O
second	O
.	O
</s>
<s>
A	O
single	O
8237	B-Device
was	O
used	O
as	O
the	O
DMA	B-General_Concept
controller	I-General_Concept
in	O
the	O
original	O
IBM	B-Device
PC	I-Device
and	O
IBM	B-Device
XT	I-Device
.	O
</s>
<s>
The	O
IBM	B-Operating_System
PC	I-Operating_System
AT	I-Operating_System
added	O
another	O
8237	B-Device
in	O
master-slave	O
configuration	O
,	O
increasing	O
the	O
number	O
of	O
DMA	O
channels	O
from	O
four	O
to	O
seven	O
.	O
</s>
<s>
Later	O
IBM-compatible	O
personal	O
computers	O
may	O
have	O
chip	O
sets	O
that	O
emulate	O
the	O
functions	O
of	O
the	O
8237	B-Device
for	O
backward	O
compatibility	O
.	O
</s>
<s>
The	O
Intel	B-Device
8237	I-Device
was	O
actually	O
designed	O
by	O
AMD	O
(	O
called	O
Am9517	O
)	O
.	O
</s>
<s>
The	O
8237	B-Device
operates	O
in	O
four	O
different	O
modes	O
,	O
depending	O
upon	O
the	O
number	O
of	O
bytes	O
transferred	O
per	O
cycle	O
and	O
number	O
of	O
ICs	O
used	O
:	O
</s>
<s>
Demand	O
-	O
Transfers	O
continue	O
until	O
TC	O
or	O
EOP	O
goes	O
active	O
or	O
DRQ	B-General_Concept
goes	O
inactive	O
.	O
</s>
<s>
Cascade	O
-	O
Used	O
to	O
cascade	O
additional	O
DMA	B-General_Concept
controllers	I-General_Concept
.	O
</s>
<s>
Channel	O
0	O
is	O
used	O
for	O
DRAM	O
refresh	O
on	O
IBM	B-Device
PC	I-Device
compatibles	O
.	O
</s>
<s>
The	O
terminal	O
count	O
(	O
TC	O
)	O
signals	O
end	O
of	O
transfer	O
to	O
ISA	B-Architecture
cards	I-Architecture
.	O
</s>
<s>
The	O
DMA	B-General_Concept
request	I-General_Concept
DREQ	O
must	O
be	O
raised	O
by	O
the	O
card	O
and	O
held	O
active	O
until	O
it	O
is	O
acknowledged	O
by	O
the	O
DMA	O
acknowledge	O
DACK	O
.	O
</s>
<s>
The	O
internal	O
registers	O
used	O
in	O
the	O
8237	B-Device
for	O
data	O
transfer	O
are	O
as	O
follows	O
:	O
</s>
<s>
As	O
a	O
member	O
of	O
the	O
Intel	O
MCS-85	O
device	O
family	O
,	O
the	O
8237	B-Device
is	O
an	O
8-bit	O
device	O
with	O
16-bit	O
addressing	O
.	O
</s>
<s>
However	O
,	O
it	O
is	O
compatible	O
with	O
the	O
8086/88	O
microprocessors	O
.	O
</s>
<s>
The	O
IBM	B-Device
PC	I-Device
and	O
PC	B-Device
XT	I-Device
models	O
(	O
machine	O
types	O
5150	O
and	O
5160	O
)	O
have	O
an	O
8088	B-Device
CPU	O
and	O
an	O
8-bit	O
system	O
bus	O
architecture	O
;	O
the	O
latter	O
interfaces	O
directly	O
to	O
the	O
8237	B-Device
,	O
but	O
the	O
8088	B-Device
has	O
a	O
20-bit	O
address	O
bus	O
,	O
so	O
four	O
additional	O
4-bit	O
address	O
latches	O
,	O
one	O
for	O
each	O
DMA	O
channel	O
,	O
are	O
added	O
alongside	O
the	O
8237	B-Device
to	O
augment	O
the	O
address	O
counters	O
.	O
</s>
<s>
However	O
,	O
because	O
these	O
external	O
latches	O
are	O
separate	O
from	O
the	O
8237	B-Device
address	O
counters	O
,	O
they	O
are	O
never	O
automatically	O
incremented	O
or	O
decremented	O
during	O
DMA	O
operations	O
,	O
making	O
it	O
impossible	O
to	O
perform	O
a	O
DMA	O
operation	O
across	O
a	O
64	O
KiB	O
address	O
boundary	O
.	O
</s>
<s>
In	O
addition	O
to	O
the	O
8237	B-Device
from	O
the	O
PC	O
and	O
XT	O
models	O
,	O
a	O
second	O
,	O
cascaded	O
8237	B-Device
is	O
added	O
,	O
for	O
16-bit	O
DMA	O
transfers	O
.	O
</s>
<s>
This	O
is	O
possible	O
,	O
despite	O
the	O
8237	B-Device
being	O
an	O
8-bit	O
device	O
,	O
because	O
the	O
8237	B-Device
performs	O
transfers	O
between	O
an	O
I/O	O
port	O
and	O
memory	O
as	O
"	O
fly-by	O
"	O
transfers	O
in	O
which	O
the	O
data	O
is	O
placed	O
onto	O
the	O
bus	O
by	O
the	O
source	O
memory	O
or	O
I/O	O
port	O
and	O
directly	O
read	O
at	O
the	O
same	O
time	O
by	O
the	O
destination	O
I/O	O
port	O
or	O
memory	O
,	O
without	O
being	O
handled	O
by	O
the	O
8237	B-Device
.	O
</s>
<s>
For	O
this	O
mode	O
of	O
transfer	O
,	O
the	O
width	O
of	O
the	O
data	O
bus	O
is	O
essentially	O
immaterial	O
to	O
the	O
8237	B-Device
(	O
as	O
long	O
as	O
it	O
is	O
connected	O
to	O
a	O
data	O
bus	O
at	O
least	O
8	O
bits	O
wide	O
,	O
for	O
programming	O
the	O
8237	B-Device
registers	O
)	O
.	O
</s>
<s>
The	O
second	O
8237	B-Device
in	O
an	O
AT-class	O
PC	O
provides	O
three	O
16-bit	O
DMA	O
channels	O
(	O
its	O
channels	O
1	O
through	O
3	O
,	O
named	O
channels	O
5	O
through	O
7	O
in	O
the	O
PCAT	O
)	O
;	O
its	O
channel0	O
(	O
named	O
channel4	O
in	O
the	O
PCAT	O
)	O
is	O
used	O
in	O
cascade	O
mode	O
to	O
connect	O
the	O
8237	B-Device
for	O
8-bit	O
DMA	O
as	O
the	O
"	O
slave	O
"	O
in	O
the	O
cascade	O
arrangement	O
;	O
the	O
8237	B-Device
providing	O
the	O
16-bit	O
channels	O
is	O
the	O
"	O
master	O
"	O
.	O
</s>
<s>
Like	O
the	O
first	O
8237	B-Device
,	O
it	O
is	O
augmented	O
with	O
four	O
address-extension	O
registers	O
.	O
</s>
<s>
Because	O
the	O
8237	B-Device
memory-to-memory	O
DMA	O
mode	O
operates	O
by	O
transferring	O
a	O
byte	O
from	O
the	O
source	O
memory	O
location	O
to	O
an	O
internal	O
temporary	O
8-bit	O
register	O
in	O
the	O
8237	B-Device
and	O
then	O
from	O
the	O
temporary	O
register	O
to	O
the	O
destination	O
memory	O
location	O
,	O
this	O
mode	O
could	O
not	O
be	O
used	O
for	O
16-bit	O
memory-to-memory	O
DMA	O
,	O
as	O
the	O
temporary	O
register	O
is	O
not	O
large	O
enough	O
.	O
</s>
<s>
Additionally	O
,	O
memory-to-memory	O
16-bit	O
DMA	O
would	O
require	O
use	O
of	O
channel	O
4	O
,	O
conflicting	O
with	O
its	O
use	O
to	O
cascade	O
the	O
8237	B-Device
that	O
handles	O
the	O
8-bit	O
DMA	O
channels	O
.	O
</s>
<s>
The	O
design	O
of	O
8237-based	O
DMA	O
in	O
PCAT	O
compatibles	O
was	O
not	O
updated	O
with	O
the	O
move	O
to	O
the	O
32-bit	O
CPUs	O
and	O
32-bit	O
system	O
bus	O
architectures	O
.	O
</s>
<s>
Consequently	O
,	O
a	O
limitation	O
on	O
these	O
machines	O
is	O
that	O
the	O
8237	B-Device
DMA	B-General_Concept
controllers	I-General_Concept
with	O
their	O
companion	O
address	O
"	O
page	O
"	O
extension	O
registers	O
only	O
can	O
address	O
16	O
MiB	O
of	O
memory	O
,	O
according	O
to	O
the	O
original	O
design	O
oriented	O
around	O
the	O
80286	O
CPU	O
,	O
which	O
itself	O
has	O
this	O
same	O
addressing	O
limitation	O
.	O
</s>
<s>
In	O
the	O
PS/2	B-Device
series	O
of	O
computers	O
,	O
IBM	O
did	O
update	O
the	O
DMA	O
hardware	O
to	O
support	O
32-bit	O
data	O
and	O
addresses	O
in	O
some	O
systems	O
with	O
80386	O
CPUs	O
,	O
but	O
they	O
did	O
this	O
by	O
replacing	O
the	O
8237	B-Device
with	O
a	O
new	O
DMA	B-General_Concept
controller	I-General_Concept
design	O
.	O
</s>
<s>
The	O
new	O
design	O
includes	O
an	O
8237	B-Device
compatibility	O
mode	O
for	O
downward	O
compatibility	O
with	O
the	O
PCAT	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
PIIX	B-Device
integrated	O
two	O
8237	B-Device
controllers	O
for	O
ISA	B-Architecture
bus	I-Architecture
DMA	O
.	O
</s>
<s>
Model	O
Number	O
Clock	O
Speed	O
Transfer	O
Speedmegabytes	O
per	O
second	O
in	O
64KB	O
block	O
Package	O
Price	O
(	O
USD	O
)	O
In	O
quantities	O
of	O
100	O
and	O
up	O
8237	B-Device
3	O
MHz	O
8237	B-Device
3	O
MHz	O
44-Pin	O
PLCCSampling	O
Q2	O
1986Ashborn	O
,	O
Jim	O
;	O
"	O
Advanced	O
Packaging	O
:	O
A	O
Little	O
Goes	O
A	O
Long	O
Way	O
"	O
,	O
Intel	O
Corporation	O
,	O
Solutions	O
,	O
January/February	O
1986	O
,	O
Page	O
2	O
8237-2	O
5	O
MHz	O
1.6	O
mps	O
$20.00	O
Intel	O
Corporation	O
,	O
"	O
Microcomputer	O
Components	O
:	O
New	O
Intel	B-Device
8237	I-Device
DMA	B-General_Concept
Controller	I-General_Concept
provides	O
a	O
5	O
MHz	O
DMA	O
answer	O
for	O
8088	B-Device
and	O
8085A-2	O
based	O
systems	O
"	O
,	O
Intel	O
Preview	O
,	O
May/June	O
1979	O
,	O
Pg	O
9	O
.	O
</s>
