<s>
The	O
Intel	B-Device
810	I-Device
chipset	B-Device
was	O
released	O
by	O
Intel	O
in	O
early	O
1999	O
with	O
the	O
code-name	O
"	O
Whitney	O
"	O
as	O
a	O
platform	O
for	O
the	O
P6-based	O
Socket	B-Device
370	I-Device
CPU	O
series	O
,	O
including	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
and	O
Celeron	B-Device
processors	O
.	O
</s>
<s>
Some	O
motherboard	O
designs	O
include	O
Slot	B-Device
1	I-Device
for	O
older	O
Intel	O
CPUs	O
or	O
a	O
combination	O
of	O
both	O
Socket	B-Device
370	I-Device
and	O
Slot	B-Device
1	I-Device
.	O
</s>
<s>
The	O
810	O
was	O
Intel	O
's	O
first	O
chipset	B-Device
design	O
to	O
incorporate	O
a	O
hub	B-Architecture
architecture	I-Architecture
which	O
was	O
claimed	O
to	O
have	O
better	O
I/O	O
throughput	O
and	O
an	O
integrated	O
GPU	O
,	O
derived	O
from	O
the	O
Intel740	B-General_Concept
.	O
</s>
<s>
810-L	O
:	O
microATX	B-Device
(	O
4	O
PCI	B-Protocol
)	O
,	O
no	O
display	O
cache	O
,	O
ATA33	B-Protocol
hard	O
disk	O
interface	O
.	O
</s>
<s>
810	O
:	O
microATX	B-Device
(	O
4	O
PCI	B-Protocol
)	O
,	O
no	O
display	O
cache	O
,	O
ATA33	B-Protocol
and	O
ATA66	B-Protocol
.	O
</s>
<s>
810-DC100	O
:	O
ATX	B-Language
(	O
6	O
PCI	B-Protocol
)	O
,	O
4	O
MB	O
display	O
cache	O
(	O
AIMM	B-Device
)	O
,	O
ATA33	B-Protocol
and	O
ATA66	B-Protocol
.	O
</s>
<s>
810E	O
:	O
added	O
support	O
for	O
133MHz	O
FSB	B-Architecture
,	O
Pentium	B-General_Concept
III	I-General_Concept
or	O
Celeron	B-Device
"	O
Coppermine-EB	O
"	O
Series	O
CPU	O
.	O
</s>
<s>
810E2:added	O
support	O
for	O
Pentium	B-General_Concept
III	I-General_Concept
and	O
Celeron	B-Device
CPUs	O
with	O
130nm	O
"	O
Tualatin	O
"	O
core	O
,	O
ATA100	O
and	O
4	O
USB	B-Protocol
1.1	O
ports	O
.	O
</s>
<s>
Intel	B-Device
810	I-Device
attempted	O
to	O
integrate	O
as	O
much	O
functionality	O
into	O
the	O
motherboard	O
as	O
possible	O
.	O
</s>
<s>
Based	O
upon	O
the	O
Intel740	B-General_Concept
2D/3D	O
accelerator	O
(	O
i752	O
)	O
.	O
</s>
<s>
Hardware	O
motion	B-Algorithm
compensation	I-Algorithm
for	O
DVD	B-Algorithm
playback	O
.	O
</s>
<s>
These	O
components	O
are	O
connected	O
by	O
a	O
separate	O
266	O
MB/s	O
bus	O
,	O
double	O
the	O
previously	O
typical	O
133	O
MB/s	O
attachment	O
via	O
PCI-Bus	B-Protocol
.	O
</s>
<s>
The	O
early	O
GMCH	O
(	O
82810	O
)	O
chips	O
(	O
A2	O
stepping	O
;	O
S-spec	O
numbers	O
can	O
be	O
found	O
on	O
the	O
fourth	O
line	O
of	O
the	O
chipset	B-Device
:	O
SL35K	O
,	O
SL35X	O
,	O
SL3KK	O
,	O
SL3KL	O
,	O
Q790	O
,	O
Q789	O
)	O
could	O
only	O
support	O
Celeron	B-Device
processors	O
as	O
they	O
were	O
unable	O
to	O
handle	O
SSE	O
instructions	O
correctly	O
.	O
</s>
<s>
810	O
supports	O
asynchronous	O
bus	O
clock	O
operation	O
between	O
the	O
chipset	B-Device
and	O
CPU	O
(	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
)	O
and	O
the	O
system	O
RAM	O
.	O
</s>
<s>
So	O
,	O
if	O
the	O
machine	O
is	O
equipped	O
with	O
a	O
Celeron	B-Device
that	O
uses	O
only	O
a	O
66MHz	O
bus	O
,	O
PC100	O
SDRAM	O
can	O
still	O
be	O
taken	O
advantage	O
of	O
and	O
will	O
benefit	O
the	O
IGP	O
.	O
</s>
<s>
Boards	O
based	O
on	O
the	O
chipset	B-Device
do	O
not	O
have	O
an	O
AGP	B-Architecture
expansion	O
slot	O
,	O
leaving	O
the	O
user	O
to	O
make	O
do	O
with	O
PCI	B-Protocol
for	O
video	O
card	O
options	O
.	O
</s>
