<s>
The	O
Intel	B-General_Concept
8085	I-General_Concept
(	O
"	O
eighty-eighty-five	O
"	O
)	O
is	O
an	O
8-bit	O
microprocessor	B-Architecture
produced	O
by	O
Intel	O
and	O
introduced	O
in	O
March	O
1976	O
.	O
</s>
<s>
It	O
is	O
software-binary	O
compatible	O
with	O
the	O
more-famous	O
Intel	B-General_Concept
8080	I-General_Concept
with	O
only	O
two	O
minor	O
instructions	O
added	O
to	O
support	O
its	O
added	O
interrupt	B-Application
and	O
serial	O
input/output	B-General_Concept
features	O
.	O
</s>
<s>
However	O
,	O
it	O
requires	O
less	O
support	O
circuitry	O
,	O
allowing	O
simpler	O
and	O
less	O
expensive	O
microcomputer	B-Architecture
systems	O
to	O
be	O
built	O
.	O
</s>
<s>
The	O
"	O
5	O
"	O
in	O
the	O
part	O
number	O
highlighted	O
the	O
fact	O
that	O
the	O
8085	B-General_Concept
uses	O
a	O
single	O
+	O
5-volt	O
(	O
V	O
)	O
power	O
supply	O
by	O
using	O
depletion-mode	B-Algorithm
transistors	B-Application
,	O
rather	O
than	O
requiring	O
the	O
+5V	O
,	O
−5V	O
and	O
+12V	O
supplies	O
needed	O
by	O
the	O
8080	B-General_Concept
.	O
</s>
<s>
This	O
capability	O
matched	O
that	O
of	O
the	O
competing	O
Z80	B-General_Concept
,	O
a	O
popular	O
8080-derived	O
CPU	O
introduced	O
the	O
year	O
before	O
.	O
</s>
<s>
These	O
processors	O
could	O
be	O
used	O
in	O
computers	O
running	O
the	O
CP/M	B-Application
operating	I-Application
system	I-Application
.	O
</s>
<s>
The	O
8085	B-General_Concept
is	O
supplied	O
in	O
a	O
40-pin	O
DIP	B-Algorithm
package	O
.	O
</s>
<s>
To	O
maximise	O
the	O
functions	O
on	O
the	O
available	O
pins	O
,	O
the	O
8085	B-General_Concept
uses	O
a	O
multiplexed	O
address/data	O
(	O
AD0-AD7	O
)	O
bus	O
.	O
</s>
<s>
However	O
,	O
an	O
8085	B-General_Concept
circuit	O
requires	O
an	O
8-bit	O
address	O
latch	O
,	O
so	O
Intel	O
manufactured	O
several	O
support	O
chips	O
with	O
an	O
address	O
latch	O
built	O
in	O
.	O
</s>
<s>
These	O
include	O
the	O
8755	O
,	O
with	O
an	O
address	O
latch	O
,	O
2	O
KB	O
of	O
EPROM	B-General_Concept
and	O
16	O
I/O	B-General_Concept
pins	O
,	O
and	O
the	O
8155	B-Device
with	O
256	O
bytes	O
of	O
RAM	O
,	O
22	O
I/O	B-General_Concept
pins	O
and	O
a	O
14-bit	O
programmable	O
timer/counter	O
.	O
</s>
<s>
The	O
multiplexed	O
address/data	O
bus	O
reduced	O
the	O
number	O
of	O
PCB	O
tracks	O
between	O
the	O
8085	B-General_Concept
and	O
such	O
memory	O
and	O
I/O	B-General_Concept
chips	O
.	O
</s>
<s>
Both	O
the	O
8080	B-General_Concept
and	O
the	O
8085	B-General_Concept
were	O
eclipsed	O
by	O
the	O
Zilog	B-General_Concept
Z80	I-General_Concept
for	O
desktop	O
computers	O
,	O
which	O
took	O
over	O
most	O
of	O
the	O
CP/M	B-Application
computer	O
market	O
,	O
as	O
well	O
as	O
a	O
share	O
of	O
the	O
booming	O
home-computer	O
market	O
in	O
the	O
early-to-mid-1980s	O
.	O
</s>
<s>
The	O
8085	B-General_Concept
had	O
a	O
long	O
life	O
as	O
a	O
controller	O
,	O
no	O
doubt	O
thanks	O
to	O
its	O
built-in	O
serial	O
I/O	B-General_Concept
and	O
five	O
prioritized	O
interrupts	B-Application
,	O
arguably	O
microcontroller-like	O
features	O
that	O
the	O
Z80	B-General_Concept
CPU	O
did	O
not	O
have	O
.	O
</s>
<s>
Once	O
designed	O
into	O
such	O
products	O
as	O
the	O
DECtape	O
II	O
controller	O
and	O
the	O
VT102	O
video	O
terminal	O
in	O
the	O
late	O
1970s	O
,	O
the	O
8085	B-General_Concept
served	O
for	O
new	O
production	O
throughout	O
the	O
lifetime	O
of	O
those	O
products	O
.	O
</s>
<s>
The	O
8085	B-General_Concept
is	O
a	O
conventional	O
von	B-Architecture
Neumann	I-Architecture
design	O
based	O
on	O
the	O
Intel	B-General_Concept
8080	I-General_Concept
.	O
</s>
<s>
Unlike	O
the	O
8080	B-General_Concept
it	O
does	O
not	O
multiplex	O
state	O
signals	O
onto	O
the	O
data	B-General_Concept
bus	I-General_Concept
,	O
but	O
the	O
8-bit	O
data	B-General_Concept
bus	I-General_Concept
is	O
instead	O
multiplexed	O
with	O
the	O
lower	O
eight	O
bits	O
of	O
the	O
16-bit	O
address	B-Architecture
bus	I-Architecture
to	O
limit	O
the	O
number	O
of	O
pins	O
to	O
40	O
.	O
</s>
<s>
The	O
processor	O
was	O
designed	O
using	O
nMOS	B-Algorithm
circuitry	O
,	O
and	O
the	O
later	O
"	O
H	O
"	O
versions	O
were	O
implemented	O
in	O
Intel	O
's	O
enhanced	O
nMOS	B-Algorithm
process	O
called	O
HMOS	O
II	O
(	O
"	O
High-performance	O
MOS	O
"	O
)	O
,	O
originally	O
developed	O
for	O
fast	O
static	O
RAM	O
products	O
.	O
</s>
<s>
Only	O
a	O
single	O
5-volt	O
power	O
supply	O
is	O
needed	O
,	O
like	O
competing	O
processors	O
and	O
unlike	O
the	O
8080	B-General_Concept
.	O
</s>
<s>
The	O
8085	B-General_Concept
uses	O
approximately	O
6,500	O
transistors	B-Application
.	O
</s>
<s>
The	O
8085	B-General_Concept
incorporates	O
the	O
functions	O
of	O
the	O
8224	O
(	O
clock	O
generator	O
)	O
and	O
the	O
8228	O
(	O
system	O
controller	O
)	O
on	O
chip	O
,	O
increasing	O
the	O
level	O
of	O
integration	O
.	O
</s>
<s>
A	O
downside	O
compared	O
to	O
similar	O
contemporary	O
designs	O
(	O
such	O
as	O
the	O
Z80	B-General_Concept
)	O
is	O
the	O
fact	O
that	O
the	O
buses	O
require	O
demultiplexing	O
;	O
however	O
,	O
address	O
latches	O
in	O
the	O
Intel	O
8155	B-Device
,	O
8355	O
,	O
and	O
8755	O
memory	O
chips	O
allow	O
a	O
direct	O
interface	O
,	O
so	O
an	O
8085	B-General_Concept
along	O
with	O
these	O
chips	O
is	O
almost	O
a	O
complete	O
system	O
.	O
</s>
<s>
The	O
8085	B-General_Concept
has	O
extensions	O
to	O
support	O
new	O
interrupts	B-Application
,	O
with	O
three	O
maskable	O
vectored	O
interrupts	B-Application
(	O
RST	O
7.5	O
,	O
RST	O
6.5	O
and	O
RST	O
5.5	O
)	O
,	O
one	O
non-maskable	B-General_Concept
interrupt	I-General_Concept
(	O
TRAP	B-Application
)	O
,	O
and	O
one	O
externally	O
serviced	O
interrupt	B-Application
(	O
INTR	O
)	O
.	O
</s>
<s>
Each	O
of	O
these	O
five	O
interrupts	B-Application
has	O
a	O
separate	O
pin	O
on	O
the	O
processor	O
,	O
a	O
feature	O
which	O
permits	O
simple	O
systems	O
to	O
avoid	O
the	O
cost	O
of	O
a	O
separate	O
interrupt	B-Architecture
controller	I-Architecture
.	O
</s>
<s>
The	O
RST	O
7.5	O
interrupt	B-Application
is	O
edge	O
triggered	O
(	O
latched	O
)	O
,	O
while	O
RST	O
5.5	O
and	O
6.5	O
are	O
level-sensitive	O
.	O
</s>
<s>
All	O
interrupts	B-Application
are	O
enabled	O
by	O
the	O
EI	O
instruction	O
and	O
disabled	O
by	O
the	O
DI	O
instruction	O
.	O
</s>
<s>
In	O
addition	O
,	O
the	O
SIM	O
(	O
Set	O
Interrupt	B-Application
Mask	I-Application
)	O
and	O
RIM	O
(	O
Read	O
Interrupt	B-Application
Mask	I-Application
)	O
instructions	O
,	O
the	O
only	O
instructions	O
of	O
the	O
8085	B-General_Concept
that	O
are	O
not	O
from	O
the	O
8080	B-General_Concept
design	O
,	O
allow	O
each	O
of	O
the	O
three	O
maskable	O
RST	O
interrupts	B-Application
to	O
be	O
individually	O
masked	O
.	O
</s>
<s>
SIM	O
and	O
RIM	O
also	O
allow	O
the	O
global	O
interrupt	B-Application
mask	I-Application
state	O
and	O
the	O
three	O
independent	O
RST	O
interrupt	B-Application
mask	I-Application
states	O
to	O
be	O
read	O
,	O
the	O
pending-interrupt	O
states	O
of	O
those	O
same	O
three	O
interrupts	B-Application
to	O
be	O
read	O
,	O
the	O
RST	O
7.5	O
trigger-latch	O
flip-flop	O
to	O
be	O
reset	O
(	O
cancelling	O
the	O
pending	O
interrupt	B-Application
without	O
servicing	O
it	O
)	O
,	O
and	O
serial	O
data	O
to	O
be	O
sent	O
and	O
received	O
via	O
the	O
SOD	O
and	O
SID	O
pins	O
,	O
respectively	O
,	O
all	O
under	O
program	O
control	O
and	O
independently	O
of	O
each	O
other	O
.	O
</s>
<s>
SIM	O
and	O
RIM	O
each	O
execute	O
in	O
four	O
clock	O
cycles	O
(	O
T	O
states	O
)	O
,	O
making	O
it	O
possible	O
to	O
sample	O
SID	O
and/or	O
toggle	O
SOD	O
considerably	O
faster	O
than	O
it	O
is	O
possible	O
to	O
toggle	O
or	O
sample	O
a	O
signal	O
via	O
any	O
I/O	B-General_Concept
or	O
memory-mapped	O
port	O
,	O
e.g.	O
</s>
<s>
one	O
of	O
the	O
port	O
of	O
an	O
8155	B-Device
.	O
</s>
<s>
(	O
In	O
this	O
way	O
,	O
SID	O
can	O
be	O
compared	O
to	O
the	O
SO	O
[	O
"	O
Set	O
Overflow	O
"	O
]	O
pin	O
of	O
the	O
6502	O
CPU	O
contemporary	O
to	O
the	O
8085	B-General_Concept
.	O
)	O
</s>
<s>
Like	O
the	O
8080	B-General_Concept
,	O
the	O
8085	B-General_Concept
can	O
accommodate	O
slower	O
memories	O
through	O
externally	O
generated	O
wait	B-Device
states	I-Device
(	O
pin	O
35	O
,	O
READY	O
)	O
,	O
and	O
has	O
provisions	O
for	O
Direct	B-General_Concept
Memory	I-General_Concept
Access	I-General_Concept
(	O
DMA	O
)	O
using	O
HOLD	O
and	O
HLDA	O
signals	O
(	O
pins	O
39	O
and	O
38	O
)	O
.	O
</s>
<s>
An	O
improvement	O
over	O
the	O
8080	B-General_Concept
is	O
that	O
the	O
8085	B-General_Concept
can	O
itself	O
drive	O
a	O
piezoelectric	O
crystal	O
directly	O
connected	O
to	O
it	O
,	O
and	O
a	O
built-in	O
clock	O
generator	O
generates	O
the	O
internal	O
high-amplitude	O
two-phase	O
clock	O
signals	O
at	O
half	O
the	O
crystal	O
frequency	O
(	O
a	O
6.14MHz	O
crystal	O
would	O
yield	O
a	O
3.07MHz	O
clock	O
,	O
for	O
instance	O
)	O
.	O
</s>
<s>
The	O
8085	B-General_Concept
can	O
also	O
be	O
clocked	O
by	O
an	O
external	O
oscillator	O
(	O
making	O
it	O
feasible	O
to	O
use	O
the	O
8085	B-General_Concept
in	O
synchronous	O
multi-processor	O
systems	O
using	O
a	O
system-wide	O
common	O
clock	O
for	O
all	O
CPUs	O
,	O
or	O
to	O
synchronize	O
the	O
CPU	O
to	O
an	O
external	O
time	O
reference	O
such	O
as	O
that	O
from	O
a	O
video	O
source	O
or	O
a	O
high-precision	O
time	O
reference	O
)	O
.	O
</s>
<s>
The	O
8085	B-General_Concept
is	O
a	O
binary	B-General_Concept
compatible	I-General_Concept
follow-up	O
on	O
the	O
8080	B-General_Concept
.	O
</s>
<s>
It	O
supports	O
the	O
complete	O
instruction	B-General_Concept
set	I-General_Concept
of	O
the	O
8080	B-General_Concept
,	O
with	O
exactly	O
the	O
same	O
instruction	O
behavior	O
,	O
including	O
all	O
effects	O
on	O
the	O
CPU	O
flags	O
(	O
except	O
for	O
the	O
AND/ANI	O
operation	O
,	O
which	O
sets	O
the	O
AC	B-Device
flag	O
differently	O
)	O
.	O
</s>
<s>
This	O
means	O
that	O
the	O
vast	O
majority	O
of	O
object	O
code	O
(	O
any	O
program	O
image	O
in	O
ROM	O
or	O
RAM	O
)	O
that	O
runs	O
successfully	O
on	O
the	O
8080	B-General_Concept
can	O
run	O
directly	O
on	O
the	O
8085	B-General_Concept
without	O
translation	O
or	O
modification	O
.	O
</s>
<s>
(	O
Exceptions	O
include	O
timing-critical	O
code	O
and	O
code	O
that	O
is	O
sensitive	O
to	O
the	O
aforementioned	O
difference	O
in	O
the	O
AC	B-Device
flag	O
setting	O
or	O
differences	O
in	O
undocumented	O
CPU	O
behavior	O
.	O
)	O
</s>
<s>
8085	B-General_Concept
instruction	O
timings	O
differ	O
slightly	O
from	O
the	O
8080	B-General_Concept
—	O
some	O
8-bit	O
operations	O
,	O
including	O
INR	O
,	O
DCR	O
,	O
and	O
the	O
heavily	O
used	O
MOV	O
r	O
,	O
r	O
 '	O
instruction	O
,	O
are	O
one	O
clock	O
cycle	O
faster	O
,	O
but	O
instructions	O
that	O
involve	O
16-bit	O
operations	O
,	O
including	O
stack	B-Application
operations	O
(	O
which	O
increment	O
or	O
decrement	O
the	O
16-bit	O
SP	O
register	O
)	O
generally	O
one	O
cycle	O
slower	O
.	O
</s>
<s>
It	O
is	O
of	O
course	O
possible	O
that	O
the	O
actual	O
8080	B-General_Concept
and/or	O
8085	B-General_Concept
differs	O
from	O
the	O
published	O
specifications	O
,	O
especially	O
in	O
subtle	O
details	O
.	O
</s>
<s>
(	O
The	O
same	O
is	O
not	O
true	O
of	O
the	O
Z80	B-General_Concept
.	O
)	O
</s>
<s>
As	O
mentioned	O
already	O
,	O
only	O
the	O
SIM	O
and	O
RIM	O
instructions	O
were	O
new	O
to	O
the	O
8085	B-General_Concept
.	O
</s>
<s>
The	O
processor	O
has	O
seven	O
8-bit	O
registers	B-General_Concept
accessible	O
to	O
the	O
programmer	O
,	O
named	O
A	O
,	O
B	O
,	O
C	B-Language
,	O
D	O
,	O
E	O
,	O
H	O
,	O
and	O
L	O
,	O
where	O
A	O
is	O
also	O
known	O
as	O
the	O
accumulator	B-General_Concept
.	O
</s>
<s>
The	O
other	O
six	O
registers	B-General_Concept
can	O
be	O
used	O
as	O
independent	O
byte-registers	O
or	O
as	O
three	O
16-bit	O
register	O
pairs	O
,	O
BC	O
,	O
DE	O
,	O
and	O
HL	O
(	O
or	O
B	O
,	O
D	O
,	O
H	O
,	O
as	O
referred	O
to	O
in	O
Intel	O
documents	O
)	O
,	O
depending	O
on	O
the	O
particular	O
instruction	O
.	O
</s>
<s>
Some	O
instructions	O
use	O
HL	O
as	O
a	O
(	O
limited	O
)	O
16-bit	O
accumulator	B-General_Concept
.	O
</s>
<s>
As	O
in	O
the	O
8080	B-General_Concept
,	O
the	O
contents	O
of	O
the	O
memory	O
address	O
pointed	O
to	O
by	O
HL	O
can	O
be	O
accessed	O
as	O
pseudo	O
register	O
M	O
.	O
It	O
also	O
has	O
a	O
16-bit	O
program	B-General_Concept
counter	I-General_Concept
and	O
a	O
16-bit	O
stack	B-General_Concept
pointer	I-General_Concept
to	O
memory	O
(	O
replacing	O
the	O
8008	O
's	O
internal	O
stack	B-Application
)	O
.	O
</s>
<s>
Instructions	O
such	O
as	O
PUSH	O
PSW	O
,	O
POP	O
PSW	O
affect	O
the	O
Program	O
Status	O
Word	O
(	O
accumulator	B-General_Concept
and	O
flags	O
)	O
.	O
</s>
<s>
The	O
accumulator	B-General_Concept
stores	O
the	O
results	O
of	O
arithmetic	O
and	O
logical	O
operations	O
,	O
and	O
the	O
flags	O
register	O
bits	O
(	O
sign	O
,	O
zero	O
,	O
auxiliary	O
carry	O
,	O
parity	O
,	O
and	O
carry	B-Algorithm
flags	I-Algorithm
)	O
are	O
set	O
or	O
cleared	O
according	O
to	O
the	O
results	O
of	O
these	O
operations	O
.	O
</s>
<s>
The	O
sign	B-Algorithm
flag	I-Algorithm
is	O
set	O
if	O
the	O
result	O
has	O
a	O
negative	O
sign	O
(	O
i.e.	O
</s>
<s>
it	O
is	O
set	O
if	O
bit	O
7	O
of	O
the	O
accumulator	B-General_Concept
is	O
set	O
)	O
.	O
</s>
<s>
The	O
auxiliary	O
or	O
half	O
carry	B-Algorithm
flag	I-Algorithm
is	O
set	O
if	O
a	O
carryover	O
from	O
bit	O
3	O
to	O
bit	O
4	O
occurred	O
.	O
</s>
<s>
The	O
parity	B-General_Concept
flag	I-General_Concept
is	O
set	O
to	O
1	O
if	O
the	O
parity	O
(	O
number	O
of	O
1-bits	O
)	O
of	O
the	O
accumulator	B-General_Concept
is	O
even	O
;	O
if	O
odd	O
,	O
it	O
is	O
cleared	O
.	O
</s>
<s>
The	O
zero	B-Algorithm
flag	I-Algorithm
is	O
set	O
if	O
the	O
result	O
of	O
the	O
operation	O
was	O
0	O
.	O
</s>
<s>
Lastly	O
,	O
the	O
carry	B-Algorithm
flag	I-Algorithm
is	O
set	O
if	O
a	O
carryover	O
from	O
bit	O
7	O
of	O
the	O
accumulator	B-General_Concept
(	O
the	O
MSB	O
)	O
occurred	O
.	O
</s>
<s>
A	O
NOP	O
"	O
no	O
operation	O
"	O
instruction	O
exists	O
,	O
but	O
does	O
not	O
modify	O
any	O
of	O
the	O
registers	B-General_Concept
or	O
flags	O
.	O
</s>
<s>
Like	O
larger	O
processors	O
,	O
it	O
has	O
CALL	O
and	O
RET	O
instructions	O
for	O
multi-level	O
procedure	O
calls	O
and	O
returns	O
(	O
which	O
can	O
be	O
conditionally	O
executed	O
,	O
like	O
jumps	O
)	O
and	O
instructions	O
to	O
save	O
and	O
restore	O
any	O
16-bit	O
register-pair	O
on	O
the	O
machine	O
stack	B-Application
.	O
</s>
<s>
These	O
are	O
intended	O
to	O
be	O
supplied	O
by	O
external	O
hardware	O
in	O
order	O
to	O
invoke	O
a	O
corresponding	O
interrupt-service	O
routine	O
,	O
but	O
are	O
also	O
often	O
employed	O
as	O
fast	O
system	O
calls	O
.	O
</s>
<s>
One	O
sophisticated	O
instruction	O
is	O
XTHL	O
,	O
which	O
is	O
used	O
for	O
exchanging	O
the	O
register	O
pair	O
HL	O
with	O
the	O
value	O
stored	O
at	O
the	O
address	O
indicated	O
by	O
the	O
stack	B-General_Concept
pointer	I-General_Concept
.	O
</s>
<s>
All	O
two-operand	O
8-bit	O
arithmetic	O
and	O
logical	O
(	O
ALU	O
)	O
operations	O
work	O
on	O
the	O
8-bit	O
accumulator	B-General_Concept
(	O
the	O
A	O
register	O
)	O
.	O
</s>
<s>
The	O
only	O
8-bit	O
ALU	O
operations	O
that	O
can	O
have	O
a	O
destination	O
other	O
than	O
the	O
accumulator	B-General_Concept
are	O
the	O
unary	O
incrementation	O
or	O
decrementation	O
instructions	O
,	O
which	O
can	O
operate	O
on	O
any	O
8-bit	O
register	O
or	O
on	O
memory	O
addressed	O
by	O
HL	O
,	O
as	O
for	O
two-operand	O
8-bit	O
operations	O
.	O
</s>
<s>
Direct	O
copying	O
is	O
supported	O
between	O
any	O
two	O
8-bit	O
registers	B-General_Concept
and	O
between	O
any	O
8-bit	O
register	O
and	O
an	O
HL-addressed	O
memory	O
cell	O
,	O
using	O
the	O
MOV	O
instruction	O
.	O
</s>
<s>
However	O
,	O
what	O
would	O
have	O
been	O
a	O
copy	O
from	O
the	O
HL-addressed	O
cell	O
into	O
itself	O
(	O
i.e.	O
,	O
MOV	O
M	O
,	O
M	O
)	O
instead	O
encodes	O
the	O
HLT	B-Language
instruction	I-Language
,	O
halting	O
execution	O
until	O
an	O
external	O
reset	O
or	O
unmasked	O
interrupt	B-Application
occurs	O
.	O
</s>
<s>
Although	O
the	O
8085	B-General_Concept
is	O
an	O
8-bit	O
processor	O
,	O
it	O
has	O
some	O
16-bit	O
operations	O
.	O
</s>
<s>
The	O
only	O
16-bit	O
instruction	O
that	O
affects	O
any	O
flag	O
is	O
DAD	O
(	O
adding	O
BC	O
,	O
DE	O
,	O
HL	O
,	O
or	O
SP	O
,	O
to	O
HL	O
)	O
,	O
which	O
updates	O
the	O
carry	B-Algorithm
flag	I-Algorithm
to	O
facilitate	O
24-bit	O
or	O
larger	O
additions	O
and	O
left	O
shifts	O
.	O
</s>
<s>
Adding	O
the	O
stack	B-General_Concept
pointer	I-General_Concept
to	O
HL	O
is	O
useful	O
for	O
indexing	O
variables	O
in	O
(	O
recursive	O
)	O
stack	B-Application
frames	O
.	O
</s>
<s>
A	O
stack	B-Application
frame	O
can	O
be	O
allocated	O
using	O
DAD	O
SP	O
and	O
SPHL	O
,	O
and	O
a	O
branch	O
to	O
a	O
computed	O
pointer	O
can	O
be	O
done	O
with	O
PCHL	O
.	O
</s>
<s>
These	O
abilities	O
make	O
it	O
feasible	O
to	O
compile	O
languages	O
such	O
as	O
PL/M	B-Language
,	O
Pascal	B-Application
,	O
or	O
C	B-Language
with	O
16-bit	O
variables	O
and	O
produce	O
8085	B-General_Concept
machine	O
code	O
.	O
</s>
<s>
A	O
number	O
of	O
undocumented	O
instructions	O
and	O
flags	O
were	O
discovered	O
by	O
two	O
software	O
engineers	O
,	O
Wolfgang	O
Dehnhardt	O
and	O
Villy	O
M	O
.	O
Sorensen	O
in	O
the	O
process	O
of	O
developing	O
an	O
8085	B-General_Concept
assembler	O
.	O
</s>
<s>
The	O
8085	B-General_Concept
supports	O
both	O
port-mapped	B-Architecture
and	I-Architecture
memory-mapped	I-Architecture
io	I-Architecture
.	O
</s>
<s>
It	O
supports	O
up	O
to	O
256	O
input/output	B-General_Concept
(	O
I/O	B-General_Concept
)	O
ports	O
via	O
dedicated	O
Input/Output	B-General_Concept
instructions	O
,	O
with	O
port	O
addresses	O
as	O
operands	O
.	O
</s>
<s>
During	O
a	O
port-mapped	O
I/O	B-General_Concept
bus	I-General_Concept
cycle	O
,	O
the	O
8-bit	O
I/O	B-Architecture
address	I-Architecture
is	O
output	O
by	O
the	O
CPU	O
on	O
both	O
the	O
lower	O
and	O
upper	O
halves	O
of	O
the	O
16-bit	O
address	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
Devices	O
designed	O
for	O
memory	B-Architecture
mapped	I-Architecture
I/O	I-Architecture
can	O
also	O
be	O
accessed	O
by	O
using	O
the	O
LDA	O
(	O
load	O
accumulator	B-General_Concept
from	O
a	O
16-bit	O
address	O
)	O
and	O
STA	O
(	O
store	O
accumulator	B-General_Concept
at	O
a	O
16-bit	O
address	O
specified	O
)	O
instructions	O
,	O
or	O
any	O
other	O
instructions	O
that	O
have	O
memory	O
operands	O
.	O
</s>
<s>
A	O
memory-mapped	B-Architecture
IO	I-Architecture
transfer	O
cycle	O
appears	O
on	O
the	O
bus	O
as	O
a	O
normal	O
memory	O
access	O
cycle	O
.	O
</s>
<s>
Intel	O
produced	O
a	O
series	O
of	O
development	O
systems	O
for	O
the	O
8080	B-General_Concept
and	O
8085	B-General_Concept
,	O
known	O
as	O
the	O
MDS-80	O
Microprocessor	B-Architecture
System	O
.	O
</s>
<s>
The	O
original	O
development	O
system	O
had	O
an	O
8080	B-General_Concept
processor	O
.	O
</s>
<s>
Later	O
8085	B-General_Concept
and	O
8086	B-General_Concept
support	O
was	O
added	O
including	O
ICE	O
(	O
in-circuit	B-Application
emulators	I-Application
)	O
.	O
</s>
<s>
It	O
runs	O
the	O
ISIS	B-Operating_System
operating	O
system	O
and	O
can	O
also	O
operate	O
an	O
emulator	B-Application
pod	O
and	O
an	O
external	O
EPROM	B-General_Concept
programmer	I-General_Concept
.	O
</s>
<s>
This	O
unit	O
uses	O
the	O
Multibus	B-Protocol
card	O
cage	O
which	O
was	O
intended	O
just	O
for	O
the	O
development	O
system	O
.	O
</s>
<s>
A	O
surprising	O
number	O
of	O
spare	O
card	O
cages	O
and	O
processors	O
were	O
being	O
sold	O
,	O
leading	O
to	O
the	O
development	O
of	O
the	O
Multibus	B-Protocol
as	O
a	O
separate	O
product	O
.	O
</s>
<s>
It	O
has	O
a	O
small	O
green	O
screen	O
,	O
a	O
keyboard	O
built	O
into	O
the	O
top	O
,	O
a	O
5¼	O
inch	O
floppy	O
disk	O
drive	O
,	O
and	O
runs	O
the	O
ISIS-II	O
operating	O
system	O
.	O
</s>
<s>
It	O
can	O
also	O
accept	O
a	O
second	O
8085	B-General_Concept
processor	O
,	O
allowing	O
a	O
limited	O
form	O
of	O
multi-processor	O
operation	O
where	O
both	O
processors	O
run	O
simultaneously	O
and	O
independently	O
.	O
</s>
<s>
It	O
has	O
a	O
bubble	B-General_Concept
memory	I-General_Concept
option	O
and	O
various	O
programming	O
modules	O
,	O
including	O
EPROM	B-General_Concept
,	O
and	O
Intel	B-Device
8048	I-Device
and	O
8051	B-Architecture
programming	O
modules	O
which	O
are	O
plugged	O
into	O
the	O
side	O
,	O
replacing	O
stand-alone	O
device	O
programmers	O
.	O
</s>
<s>
In	O
addition	O
to	O
an	O
8080/8085	O
assembler	O
,	O
Intel	O
produced	O
a	O
number	O
of	O
compilers	O
including	O
those	O
for	O
PL/M	B-Language
-80	I-Language
and	O
Pascal	B-Application
,	O
and	O
a	O
set	O
of	O
tools	O
for	O
linking	O
and	O
statically	O
locating	O
programs	O
to	O
enable	O
them	O
to	O
be	O
burned	O
into	O
EPROMs	B-General_Concept
and	O
used	O
in	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
A	O
lower	O
cost	O
"	O
MCS-85	B-General_Concept
System	O
Design	O
Kit	O
"	O
(	O
SDK-85	O
)	O
board	O
contains	O
an	O
8085	B-General_Concept
CPU	O
,	O
an	O
8355	O
ROM	O
containing	O
a	O
debugging	O
monitor	O
program	O
,	O
an	O
8155	B-Device
RAM	O
and	O
22	O
I/O	B-Architecture
ports	I-Architecture
,	O
an	O
8279	B-Device
hex	O
keypad	O
and	O
8-digit	O
7-segment	O
LED	O
,	O
and	O
a	O
TTY	O
(	O
Teletype	O
)	O
current	O
loop	O
serial	O
interface	O
.	O
</s>
<s>
Pads	O
are	O
available	O
for	O
one	O
more	O
2K×8	O
8755	O
EPROM	B-General_Concept
,	O
and	O
another	O
RAM	O
8155	B-Device
I/O	B-General_Concept
Timer/Counter	O
can	O
be	O
optionally	O
added	O
.	O
</s>
<s>
Model	O
Number	O
Technology	O
Process	O
Process	O
Node	O
Clock	O
Speed	O
Temperature	O
Range	O
Current	O
Rating	O
Power	O
Tolerance	O
Package	O
Date	O
of	O
Release	O
Price	O
USDIn	O
quantities	O
of	O
100	O
and	O
up	O
8085A	O
NMOS	B-Algorithm
3	O
micron	O
3	O
MHz	O
170	O
mA	O
±	O
5%	O
$6.25	O
P8085AH	O
HMOS	O
II	O
2	O
micron	O
3	O
MHz	O
135	O
mA	O
±	O
10%	O
Plastic	O
July/August	O
1981	O
$4.40	O
8085-2Intel	O
Corporation	O
,	O
"	O
New	O
EPROM	B-General_Concept
completes	O
5MHz	O
capability	O
for	O
MCS-85	B-General_Concept
™	O
family	O
"	O
,	O
Intel	O
Preview	O
,	O
January/February	O
1980	O
,	O
p	B-General_Concept
.	O
24	O
.	O
</s>
<s>
5	O
MHz	O
8085A-2	O
NMOS	B-Algorithm
3	O
micron	O
5	O
MHz	O
170	O
mA	O
±	O
5%	O
$8.75	O
P8085AH-2	O
HMOS	O
II	O
2	O
micron	O
5	O
MHz	O
135	O
mA	O
±	O
10%	O
Plastic	O
July/August	O
1981	O
$5.80	O
P8085AH-1	O
HMOS	O
II	O
2	O
micron	O
6	O
MHz	O
Plastic	O
July/August	O
1981	O
$12.45	O
ID8085Intel	O
Corporation	O
,	O
"	O
Microcomputer	B-Architecture
Component	O
:	O
New	O
industrial	O
grade	O
product	O
line	O
answers	O
the	O
demand	O
for	O
high-reliability	O
components	O
to	O
operate	O
in	O
industrial	O
applications	O
.	O
</s>
<s>
"	O
,	O
Intel	O
Preview	O
,	O
March/April	O
1979	O
,	O
p	B-General_Concept
.	O
11	O
.	O
</s>
<s>
"	O
,	O
Intel	O
Preview	O
,	O
March/April	O
1979	O
,	O
p	B-General_Concept
.	O
19	O
.	O
</s>
<s>
The	O
8085	B-General_Concept
processor	O
was	O
used	O
in	O
a	O
few	O
early	O
personal	O
computers	O
,	O
for	O
example	O
,	O
the	O
TRS-80	B-Operating_System
Model	I-Operating_System
100	I-Operating_System
line	I-Operating_System
used	O
an	O
OKI	O
manufactured	O
80C85	B-General_Concept
(	O
MSM80C85ARS	O
)	O
.	O
</s>
<s>
The	O
CMOS	B-Device
version	O
80C85	B-General_Concept
of	O
the	O
NMOS/HMOS	O
8085	B-General_Concept
processor	O
has	O
several	O
manufacturers	O
.	O
</s>
<s>
In	O
the	O
Soviet	O
Union	O
,	O
an	O
80C85	B-General_Concept
clone	O
was	O
developed	O
under	O
the	O
designation	O
IM1821VM85A	O
(	O
)	O
2016	O
was	O
still	O
in	O
production	O
.	O
</s>
<s>
The	O
radiation	O
hardened	O
version	O
of	O
the	O
8085	B-General_Concept
has	O
been	O
in	O
on-board	O
instrument	O
data	O
processors	O
for	O
several	O
NASA	O
and	O
ESA	O
space	O
physics	O
missions	O
in	O
the	O
1990s	O
and	O
early	O
2000s	O
,	O
including	O
CRRES	O
,	O
Polar	O
,	O
FAST	O
,	O
Cluster	O
,	O
HESSI	O
,	O
the	O
Sojourner	O
Mars	O
Rover	O
,	O
and	O
THEMIS	O
.	O
</s>
<s>
The	O
Swiss	O
company	O
SAIA	O
used	O
the	O
8085	B-General_Concept
and	O
the	O
8085-2	O
as	O
the	O
CPUs	O
of	O
their	O
PCA1	O
line	O
of	O
programmable	B-Architecture
logic	I-Architecture
controllers	I-Architecture
during	O
the	O
1980s	O
.	O
</s>
<s>
Pro-Log	O
Corp	O
.	O
put	O
the	O
8085	B-General_Concept
and	O
supporting	O
hardware	O
on	O
an	O
STD	O
Bus	O
format	O
card	O
containing	O
CPU	O
,	O
RAM	O
,	O
sockets	O
for	O
ROM/EPROM	O
,	O
I/O	B-General_Concept
and	O
external	O
bus	O
interfaces	O
.	O
</s>
<s>
The	O
included	O
Instruction	B-General_Concept
Set	I-General_Concept
Reference	O
Card	O
uses	O
entirely	O
different	O
mnemonics	O
for	O
the	O
Intel	B-General_Concept
8085	I-General_Concept
CPU	O
.	O
</s>
<s>
The	O
product	O
was	O
a	O
direct	O
competitor	O
to	O
Intel	O
's	O
Multibus	B-Protocol
card	O
offerings	O
.	O
</s>
<s>
The	O
8085	B-General_Concept
CPU	O
is	O
one	O
part	O
of	O
a	O
family	O
of	O
chips	O
developed	O
by	O
Intel	O
for	O
building	O
a	O
complete	O
system	O
.	O
</s>
<s>
The	O
original	O
IBM	B-Device
PC	I-Device
based	O
on	O
the	O
Intel	O
8088	O
processor	O
used	O
several	O
of	O
these	O
chips	O
;	O
the	O
equivalent	O
functions	O
today	O
are	O
provided	O
by	O
VLSI	O
chips	O
,	O
namely	O
the	O
"	O
Southbridge	B-Device
"	O
chips	O
.	O
</s>
<s>
8155	B-Device
–	O
2K-bit	O
static	O
MOS	O
RAM	O
with	O
3	O
I/O	B-Architecture
Ports	I-Architecture
and	O
Timer	O
.	O
</s>
<s>
There	O
is	O
a	O
version	O
of	O
Intel	O
8155-2	O
.	O
</s>
<s>
8156	O
–	O
2K-bit	O
static	O
MOS	O
RAM	O
with	O
3	O
I/O	B-Architecture
Ports	I-Architecture
and	O
Timer	O
.	O
</s>
<s>
8355	O
–	O
2,048	O
×	O
8-bit	O
ROM	O
,	O
two	O
8-bit	O
I/O	B-Architecture
ports	I-Architecture
.	O
</s>
<s>
8755	O
–	O
2048	O
x	O
8-bit	O
EPROM	B-General_Concept
,	O
two	O
8-bit	O
I/O	B-Architecture
ports	I-Architecture
.	O
</s>
<s>
The	O
Intel	O
82C03	O
CMOS	B-Device
version	O
dissipates	O
less	O
than	O
25	O
mA	O
.	O
</s>
<s>
8212	O
–	O
8-bit	O
I/O	B-Architecture
Port	I-Architecture
.	O
</s>
<s>
8254	B-Device
–	O
Programmable	B-Device
Interval	I-Device
Timer	I-Device
.	O
</s>
<s>
The	O
82C54	O
CMOS	B-Device
version	O
was	O
outsourced	O
to	O
Oki	O
Electronic	O
Industry	O
Co.	O
,	O
Ltd	O
.	O
</s>
<s>
This	O
multifunction	O
chip	O
uses	O
Serial	O
Communications	O
,	O
Parallel	B-Operating_System
I/O	I-Operating_System
,	O
Counter/Timers	O
and	O
Interrupts	B-Application
.	O
</s>
<s>
Intel	B-Device
8259A	I-Device
Programmable	B-Architecture
Interrupt	I-Architecture
Controller	I-Architecture
.	O
</s>
<s>
8272	B-Device
–	O
Single/Double	O
Density	O
Floppy	B-Device
Disk	I-Device
Controller	I-Device
.	O
</s>
<s>
It	O
is	O
compatible	O
with	O
IBM	B-Device
3740	I-Device
and	O
System	B-Device
34	I-Device
formats	O
and	O
provides	O
both	O
Frequency	B-Application
Modulation	I-Application
(	O
FM	B-Protocol
)	O
or	O
Modified	B-Protocol
Frequency	I-Protocol
Modulation	I-Protocol
(	O
MFM	B-Protocol
)	O
.	O
</s>
<s>
8273	O
–	O
Programmable	O
HDLC/SDLC	O
Protocol	O
Controller	O
.	O
</s>
<s>
This	O
device	O
supports	O
ISO/CCITT	O
'	O
s	B-Algorithm
HDLC	O
and	O
IBM	O
's	O
SDLC	B-Protocol
communication	O
protocols	O
.	O
</s>
<s>
The	O
Byte	O
Synchronous	O
mode	O
is	O
compatible	O
to	O
IBM	O
's	O
Bisync	B-Protocol
signal	O
protocol	O
.	O
</s>
<s>
The	O
Bit	O
Synchronous	O
mode	O
is	O
compatible	O
to	O
IBM	O
's	O
SDLC	B-Protocol
and	O
the	O
International	O
Standards	O
Organization	O
's	O
HDLC	O
protocol	O
and	O
is	O
compatible	O
with	O
CCITT	B-Protocol
X.25	I-Protocol
international	O
standard	O
as	O
well	O
.	O
</s>
<s>
It	O
was	O
packaged	O
in	O
40-pin	O
product	O
using	O
the	O
Intel	O
's	O
HMOS	O
technology	O
.	O
</s>
<s>
8294	O
–	O
Data	O
Encryption/Decryption	O
Unit	O
+	O
1	O
O/P	O
Port	O
.	O
</s>
<s>
In	O
many	O
engineering	O
schools	O
the	O
8085	B-General_Concept
processor	O
is	O
used	O
in	O
introductory	O
microprocessor	B-Architecture
courses	O
.	O
</s>
<s>
Trainer	O
kits	O
composed	O
of	O
a	O
printed	O
circuit	O
board	O
,	O
8085	B-General_Concept
,	O
and	O
supporting	O
hardware	O
are	O
offered	O
by	O
various	O
companies	O
.	O
</s>
<s>
Also	O
,	O
the	O
architecture	O
and	O
instruction	B-General_Concept
set	I-General_Concept
of	O
the	O
8085	B-General_Concept
are	O
easy	O
for	O
a	O
student	O
to	O
understand	O
.	O
</s>
<s>
Shared	O
Project	O
versions	O
of	O
educational	O
and	O
hobby	O
8085-based	O
single-board	B-Device
computers	I-Device
are	O
noted	O
below	O
in	O
the	O
External	O
Links	O
section	O
of	O
this	O
article	O
.	O
</s>
<s>
Software	O
simulators	O
are	O
available	O
for	O
the	O
8085	B-General_Concept
microprocessor	B-Architecture
,	O
which	O
allow	O
simulated	O
execution	O
of	O
opcodes	O
in	O
a	O
graphical	O
environment	O
.	O
</s>
