<s>
Intel	B-Device
5	I-Device
Series	I-Device
is	O
a	O
computing	O
architecture	O
introduced	O
in	O
2008	O
that	O
improves	O
the	O
efficiency	O
and	O
balances	O
the	O
use	O
of	O
communication	O
channels	O
in	O
the	O
motherboard	B-Device
.	O
</s>
<s>
The	O
architecture	O
consists	O
primarily	O
of	O
a	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
(	O
connected	O
to	O
the	O
graphics	O
card	O
and	O
memory	O
)	O
and	O
a	O
single	O
chipset	B-Device
(	O
connected	O
to	O
motherboard	B-Device
components	O
)	O
.	O
</s>
<s>
All	O
motherboard	B-Device
communications	O
and	O
activities	O
circle	O
around	O
these	O
two	O
devices	O
.	O
</s>
<s>
The	O
architecture	O
is	O
a	O
product	O
of	O
adjustments	O
made	O
to	O
the	O
Intel	O
4	O
Series	O
to	O
deliver	O
higher	O
performance	O
motherboards	B-Device
while	O
maintaining	O
efficiency	O
and	O
low	O
power	O
.	O
</s>
<s>
The	O
changes	O
revolve	O
around	O
chipset	B-Device
and	O
processor	O
design	O
,	O
in	O
conjunction	O
with	O
a	O
rearrangement	O
of	O
functions	O
and	O
controllers	O
.	O
</s>
<s>
The	O
concept	O
of	O
the	O
architecture	O
was	O
to	O
improve	O
motherboard	B-Device
mechanics	O
to	O
keep	O
pace	O
with	O
the	O
CPU	O
as	O
it	O
gained	O
more	O
speed	O
and	O
multiplied	O
in	O
number	O
of	O
cores	O
.	O
</s>
<s>
In	O
the	O
previous	O
architecture	O
,	O
the	O
CPU	O
was	O
communicating	O
heavily	O
with	O
the	O
motherboard	B-Device
's	O
central	O
component	O
,	O
the	O
Northbridge	B-Device
chipset	B-Device
,	O
as	O
it	O
was	O
the	O
intermediary	O
between	O
the	O
CPU	O
,	O
memory	O
,	O
and	O
,	O
in	O
most	O
cases	O
,	O
graphics	O
card	O
.	O
</s>
<s>
The	O
CPU	O
would	O
communicate	O
with	O
the	O
Northbridge	B-Device
chipset	B-Device
when	O
it	O
needed	O
data	O
from	O
the	O
memory	O
or	O
when	O
it	O
needed	O
to	O
output	O
graphics	O
to	O
the	O
display	O
.	O
</s>
<s>
This	O
arrangement	O
caused	O
the	O
communication	O
channel	O
known	O
as	O
the	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
to	O
be	O
heavily	O
used	O
.	O
</s>
<s>
With	O
the	O
memory	O
controller	O
and/or	O
graphics	O
core	O
moved	O
into	O
the	O
processor	O
,	O
the	O
reliance	O
of	O
separate	O
motherboard	B-Device
chipsets	B-Device
for	O
these	O
functions	O
are	O
reduced	O
.	O
</s>
<s>
The	O
Ibex	O
Peak	O
chipset	B-Device
includes	O
only	O
Platform	B-Device
Controller	I-Device
Hub	I-Device
(	O
PCH	O
)	O
per	O
model	O
,	O
which	O
provides	O
peripheral	O
connections	O
,	O
and	O
display	O
controllers	O
for	O
CPU	O
with	O
integrated	O
graphics	O
via	O
Flexible	B-Device
Display	I-Device
Interface	I-Device
(	O
excluding	O
P-models	O
)	O
.	O
</s>
<s>
Additionally	O
,	O
the	O
PCH	O
is	O
connected	O
to	O
the	O
CPU	O
via	O
Direct	B-Architecture
Media	I-Architecture
Interface	I-Architecture
(	O
DMI	B-Architecture
)	O
.	O
</s>
<s>
Taking	O
advantage	O
of	O
Intel	B-Device
Nehalem	I-Device
CPUs	O
with	O
integrated	O
graphics	O
and	O
PCI	B-Protocol
Express	O
ports	O
,	O
the	O
Intel	B-Device
Management	I-Device
Engine	I-Device
(	O
ME	O
)	O
and	O
a	O
display	O
controller	O
for	O
integrated	O
graphics	O
,	O
once	O
housed	O
in	O
north	B-Device
bridge	I-Device
,	O
are	O
moved	O
into	O
the	O
Platform	B-Device
Controller	I-Device
Hub	I-Device
(	O
PCH	O
)	O
.	O
</s>
<s>
The	O
I/O	B-Device
Controller	I-Device
Hub	I-Device
(	O
ICH	O
)	O
function	O
is	O
integrated	O
into	O
the	O
PCH	O
,	O
removing	O
the	O
need	O
for	O
separate	O
north	B-Device
bridge	I-Device
and	O
south	B-Device
bridge	I-Device
.	O
</s>
<s>
The	O
Tylersburg	O
family	O
of	O
chipsets	B-Device
is	O
for	O
Socket	O
LGA	B-Device
1366	I-Device
supporting	O
CPUs	O
with	O
triple	O
channel	O
memory	O
controllers	O
.	O
</s>
<s>
Unlike	O
the	O
Ibex	O
Peak	O
chipsets	B-Device
,	O
The	O
Tylersburg	O
family	O
of	O
chipsets	B-Device
do	O
not	O
include	O
the	O
PCH	O
,	O
and	O
the	O
I/O	O
Hub	O
mainly	O
provides	O
extra	O
PCI	B-Protocol
Express	O
2.0	O
ports	O
.	O
</s>
<s>
Peripheral	O
connections	O
are	O
provided	O
by	O
I/O	B-Device
Controller	I-Device
Hub	I-Device
(	O
ICH	O
)	O
connected	O
to	O
the	O
DMI	B-Architecture
interface	O
.	O
</s>
<s>
Intel	B-Device
5	I-Device
series	I-Device
IOH	O
support	O
ICH10	O
,	O
while	O
Intel	O
5500	O
Series	O
IOH	O
support	O
ICH9	O
or	O
ICH10	O
.	O
</s>
<s>
1	O
Nehalem	B-Device
moves	O
the	O
memory	O
controller	O
into	O
the	O
processor	O
,	O
thereby	O
obsoleting	O
the	O
north	B-Device
bridge	I-Device
.	O
</s>
<s>
Despite	O
that	O
,	O
LGA	B-Device
1366	I-Device
still	O
features	O
a	O
north	O
and	O
a	O
south	B-Device
bridge	I-Device
.	O
</s>
<s>
The	O
X58	B-Device
IOH	O
acts	O
as	O
a	O
bridge	O
from	O
the	O
QPI	B-Architecture
to	O
PCI	B-Protocol
Express	O
peripherals	O
and	O
DMI	B-Architecture
to	O
the	O
ICH10/ICH10R	O
southbridge	B-Device
.	O
</s>
<s>
2	O
X58	B-Device
TDP	B-General_Concept
includes	O
the	O
X58	B-Device
IOH	O
TDP	B-General_Concept
in	O
addition	O
to	O
the	O
ICH10/ICH10R	O
TDP	B-General_Concept
.	O
</s>
<s>
The	O
Nehalem-based	O
Xeons	O
for	O
dual-socket	O
systems	O
,	O
initially	O
launched	O
as	O
the	O
Xeon	O
55xx	O
series	O
,	O
feature	O
a	O
very	O
different	O
system	O
structure	O
:	O
the	O
memory	O
controllers	O
are	O
on	O
the	O
CPU	O
,	O
and	O
the	O
CPUs	O
can	O
communicate	O
with	O
one	O
another	O
as	O
peers	O
without	O
going	O
via	O
the	O
chipset	B-Device
.	O
</s>
