<s>
The	O
Intel	B-General_Concept
4004	I-General_Concept
is	O
a	O
4-bit	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
released	O
by	O
Intel	O
Corporation	O
in	O
1971	O
.	O
</s>
<s>
Sold	O
for	O
US$60	O
,	O
it	O
was	O
the	O
first	O
commercially	O
produced	O
microprocessor	B-Architecture
,	O
and	O
the	O
first	O
in	O
a	O
long	B-Device
line	I-Device
of	I-Device
Intel	I-Device
CPUs	I-Device
.	O
</s>
<s>
The	O
4004	B-General_Concept
was	O
the	O
first	O
significant	O
example	O
of	O
large	O
scale	O
integration	O
,	O
showcasing	O
the	O
superiority	O
of	O
the	O
MOS	O
silicon	O
gate	O
technology	O
(	O
SGT	O
)	O
.	O
</s>
<s>
The	O
innovative	O
4004	B-General_Concept
chip	O
design	O
served	O
as	O
a	O
model	O
on	O
how	O
to	O
use	O
the	O
SGT	O
for	O
complex	O
logic	O
and	O
memory	O
circuits	O
,	O
thus	O
accelerating	O
the	O
adoption	O
of	O
the	O
SGT	O
by	O
the	O
world	O
’s	O
semiconductor	O
industry	O
.	O
</s>
<s>
He	O
later	O
used	O
the	O
SGT	O
at	O
Intel	O
to	O
obtain	O
the	O
unprecedented	O
integration	O
necessary	O
to	O
make	O
the	O
first	O
single	O
chip	O
microprocessor	B-Architecture
.	O
</s>
<s>
The	O
CPU	O
was	O
based	O
on	O
data	O
stored	O
on	O
shift-registers	B-General_Concept
and	O
instructions	O
stored	O
on	O
ROM	O
(	O
read	O
only	O
memory	O
)	O
.	O
</s>
<s>
The	O
complexity	O
of	O
the	O
three-chip	O
CPU	O
logic	O
design	O
led	O
Marcian	O
Hoff	O
to	O
propose	O
a	O
more	O
conventional	O
CPU	O
architecture	O
based	O
on	O
data	O
stored	O
on	O
RAM	B-Architecture
(	O
random	B-Architecture
access	I-Architecture
memory	I-Architecture
)	O
.	O
</s>
<s>
The	O
first	O
delivery	O
of	O
a	O
fully	O
operational	O
4004	B-General_Concept
was	O
in	O
March	O
1971	O
to	O
Busicom	O
for	O
its	O
141-PF	O
printing	O
calculator	O
engineering	O
prototype	O
(	O
now	O
displayed	O
in	O
the	O
Computer	O
History	O
Museum	O
in	O
Mountain	O
View	O
,	O
California	O
)	O
.	O
</s>
<s>
A	O
number	O
of	O
innovations	O
developed	O
by	O
Faggin	O
while	O
working	O
at	O
Fairchild	O
Semiconductor	O
allowed	O
the	O
4004	B-General_Concept
to	O
be	O
produced	O
on	O
a	O
single	O
chip	O
.	O
</s>
<s>
To	O
make	O
the	O
4004	B-General_Concept
possible	O
,	O
Faggin	O
also	O
developed	O
the	O
"	O
bootstrap	O
load	O
"	O
,	O
considered	O
unfeasible	O
with	O
silicon	O
gate	O
,	O
and	O
the	O
"	O
buried	O
contact	O
"	O
that	O
allowed	O
the	O
silicon	O
gates	O
to	O
be	O
connected	O
directly	O
to	O
the	O
source	O
and	O
drain	O
of	O
the	O
transistors	O
without	O
the	O
use	O
of	O
metal	O
.	O
</s>
<s>
The	O
4004	B-General_Concept
design	O
was	O
later	O
improved	O
by	O
Faggin	O
as	O
the	O
Intel	B-General_Concept
4040	I-General_Concept
in	O
1974	O
.	O
</s>
<s>
The	O
Intel	B-General_Concept
8008	I-General_Concept
and	O
8080	B-General_Concept
were	O
unrelated	O
designs	O
in	O
spite	O
of	O
the	O
similar	O
naming	O
.	O
</s>
<s>
They	O
based	O
their	O
design	O
on	O
the	O
architecture	O
of	O
the	O
1965	O
Olivetti	O
Programma	O
101	O
,	O
one	O
of	O
the	O
world	O
's	O
first	O
tabletop	O
programmable	B-Application
calculators	I-Application
.	O
</s>
<s>
The	O
key	O
difference	O
was	O
that	O
the	O
Busicom	O
design	O
would	O
use	O
integrated	O
circuits	O
to	O
replace	O
the	O
printed	O
circuit	O
boards	O
filled	O
with	O
individual	O
components	O
,	O
and	O
solid-state	O
shift	B-General_Concept
registers	I-General_Concept
for	O
memory	O
instead	O
of	O
the	O
costly	O
magnetostriction	O
wire	O
in	O
the	O
101	O
.	O
</s>
<s>
The	O
company	O
had	O
already	O
produced	O
a	O
calculator	O
using	O
TTL	B-General_Concept
small	O
scale	O
integration	O
logic	O
ICs	O
and	O
were	O
interested	O
in	O
having	O
Intel	O
reduce	O
the	O
chip	O
count	O
using	O
Intel	O
's	O
medium	O
scale	O
integration	O
(	O
MSI	O
)	O
techniques	O
.	O
</s>
<s>
Their	O
initial	O
proposal	O
had	O
seven	O
ICs	O
,	O
program	O
control	O
,	O
arithmetic	O
unit	O
(	O
ALU	O
)	O
,	O
timing	O
,	O
program	O
ROM	O
,	O
shift	B-General_Concept
registers	I-General_Concept
for	O
temporary	O
memory	O
,	O
printer	O
controller	O
and	O
input/output	B-General_Concept
control	O
.	O
</s>
<s>
The	O
original	O
idea	O
was	O
that	O
the	O
company	O
could	O
use	O
the	O
same	O
chips	O
with	O
different	O
amounts	O
of	O
shift	B-General_Concept
register	I-General_Concept
RAM	B-Architecture
and	O
program	O
ROM	O
to	O
produce	O
a	O
range	O
of	O
calculating	O
machines	O
.	O
</s>
<s>
Hoff	O
was	O
struck	O
by	O
how	O
closely	O
the	O
Busicom	O
's	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
matched	O
that	O
of	O
general-purpose	O
computers	O
.	O
</s>
<s>
When	O
later	O
asked	O
where	O
he	O
got	O
the	O
ideas	O
for	O
the	O
architecture	O
of	O
the	O
first	O
microprocessor	B-Architecture
,	O
Hoff	O
related	O
that	O
Plessey	O
,	O
"	O
a	O
British	O
tractor	O
company	O
"	O
,	O
had	O
donated	O
a	O
minicomputer	B-Architecture
to	O
Stanford	O
,	O
and	O
he	O
had	O
"	O
played	O
with	O
it	O
some	O
"	O
while	O
he	O
was	O
there	O
.	O
</s>
<s>
Another	O
development	O
that	O
allowed	O
this	O
design	O
to	O
be	O
made	O
practical	O
was	O
Intel	O
's	O
work	O
on	O
the	O
earliest	O
dynamic	O
RAM	B-Architecture
(	O
DRAM	O
)	O
chips	O
.	O
</s>
<s>
Shift	B-General_Concept
registers	I-General_Concept
at	O
that	O
time	O
were	O
among	O
the	O
only	O
low-cost	O
read	O
and	O
write	O
memory	O
devices	O
.	O
</s>
<s>
The	O
time	O
to	O
retrieve	O
any	O
given	O
data	O
,	O
one	O
byte	B-Application
for	O
instance	O
,	O
is	O
a	O
function	O
of	O
the	O
clock	O
speed	O
and	O
the	O
number	O
of	O
cells	O
in	O
a	O
chain	O
.	O
</s>
<s>
Another	O
was	O
that	O
the	O
design	O
did	O
not	O
feature	O
any	O
sort	O
of	O
interrupt	B-Application
so	O
dealing	O
with	O
real-time	O
events	O
would	O
be	O
difficult	O
.	O
</s>
<s>
To	O
address	O
the	O
complexity	O
of	O
the	O
subroutines	O
,	O
originally	O
solved	O
in	O
Busicom	O
's	O
design	O
using	O
one	O
byte	B-Application
macroinstructions	O
and	O
complex	O
decoder	O
circuitry	O
,	O
Mazor	O
developed	O
a	O
20-byte	O
long	O
interpreter	B-Application
that	O
executed	O
the	O
same	O
macroinstructions	O
.	O
</s>
<s>
Shima	O
suggested	O
adding	O
a	O
new	O
interrupt	B-Application
that	O
would	O
be	O
triggered	O
by	O
a	O
pin	O
,	O
thereby	O
allowing	O
the	O
keyboard	O
to	O
be	O
interrupt	B-Application
driven	O
.	O
</s>
<s>
He	O
also	O
modified	O
the	O
Branch	O
Back	O
(	O
return	O
from	O
subroutine	O
)	O
instruction	O
to	O
clear	O
the	O
accumulator	B-General_Concept
.	O
</s>
<s>
As	O
data	O
was	O
4-bits	O
and	O
the	O
address	B-General_Concept
space	I-General_Concept
was	O
12-bits	O
(	O
4096	O
bytes	B-Application
)	O
,	O
there	O
was	O
no	O
way	O
direct	O
access	O
could	O
be	O
arranged	O
with	O
anything	O
fewer	O
than	O
about	O
24-pins	O
.	O
</s>
<s>
This	O
was	O
not	O
small	O
enough	O
,	O
so	O
the	O
design	O
would	O
use	O
a	O
16-pin	O
dual	B-Algorithm
in-line	I-Algorithm
package	I-Algorithm
(	O
DIP	B-Algorithm
)	O
layout	O
and	O
use	O
multiplexing	B-Architecture
of	O
a	O
single	O
set	O
of	O
4	O
lines	O
.	O
</s>
<s>
The	O
result	O
of	O
the	O
discussions	O
between	O
Intel	O
and	O
Busicom	O
was	O
an	O
architecture	O
that	O
reduced	O
the	O
7-chip	O
Busicom	O
design	O
to	O
a	O
4-chip	O
Intel	O
proposal	O
composed	O
of	O
CPU	O
,	O
ROM	O
,	O
RAM	B-Architecture
and	O
I/O	B-General_Concept
(	O
input-output	B-General_Concept
)	O
devices	O
.	O
</s>
<s>
The	O
silicon	O
gate	O
technology	O
also	O
reduced	O
the	O
leakage	O
current	O
by	O
more	O
than	O
100	O
times	O
,	O
making	O
possible	O
sophisticated	O
dynamic	O
circuits	O
like	O
DRAMs	O
(	O
dynamic	O
random	B-Architecture
access	I-Architecture
memories	I-Architecture
)	O
.	O
</s>
<s>
It	O
also	O
allowed	O
the	O
highly-doped	O
silicon	O
used	O
for	O
the	O
gates	O
to	O
form	O
the	O
interconnections	O
,	O
greatly	O
improving	O
the	O
circuit	O
density	O
of	O
random-logic	O
ICs	O
like	O
microprocessors	B-Architecture
.	O
</s>
<s>
Previously	O
the	O
interconnects	B-General_Concept
had	O
to	O
be	O
much	O
larger	O
than	O
required	O
in	O
order	O
to	O
ensure	O
the	O
aluminum	O
touched	O
the	O
silicon	O
components	O
which	O
would	O
be	O
offset	O
due	O
to	O
inaccuracies	O
in	O
the	O
machinery	O
.	O
</s>
<s>
The	O
four	O
chips	O
were	O
the	O
following	O
:	O
the	O
4001	O
,	O
256-byte	O
4-bit	O
ROM	O
;	O
the	O
4002	O
,	O
DRAM	O
with	O
four	O
20-nibble	O
registers	O
;	O
the	O
4003	O
,	O
I/O	B-General_Concept
with	O
a	O
10-bit	O
static	O
shift	B-General_Concept
register	I-General_Concept
with	O
serial	O
and	O
parallel	O
outputs	O
;	O
and	O
the	O
4004	B-General_Concept
CPU	O
.	O
</s>
<s>
A	O
fully	O
expanded	O
system	O
could	O
support	O
16	O
4001	O
's	O
for	O
a	O
total	O
of	O
4kB	O
of	O
ROM	O
,	O
16	O
4002	O
's	O
for	O
a	O
total	O
of	O
1,280	O
nibbles	O
(	O
640	O
)	O
bytes	B-Application
of	O
RAM	B-Architecture
,	O
and	O
an	O
unlimited	O
number	O
of	O
4003	O
's	O
.	O
</s>
<s>
The	O
4003	O
's	O
were	O
connected	O
to	O
programmable	O
input	B-General_Concept
and	I-General_Concept
output	I-General_Concept
pins	O
on	O
the	O
4001	O
and	O
to	O
output	O
pins	O
on	O
the	O
4002	O
,	O
not	O
directly	O
to	O
the	O
CPU	O
.	O
</s>
<s>
The	O
first	O
wafers	B-Architecture
of	O
the	O
4001	O
were	O
processed	O
in	O
October	O
1970	O
,	O
followed	O
by	O
the	O
4003	O
and	O
4002	O
in	O
November	O
.	O
</s>
<s>
The	O
first	O
4004s	B-General_Concept
arrived	O
at	O
the	O
end	O
of	O
December	O
,	O
and	O
were	O
completely	O
non-functional	O
.	O
</s>
<s>
A	O
second	O
run	O
was	O
fabricated	O
in	O
January	O
1971	O
and	O
the	O
4004	B-General_Concept
worked	O
perfectly	O
except	O
for	O
two	O
minor	O
problems	O
.	O
</s>
<s>
It	O
consisted	O
of	O
one	O
4004	B-General_Concept
,	O
two	O
4002	O
,	O
three	O
4003	O
,	O
and	O
four	O
4001	O
chips	O
.	O
</s>
<s>
With	O
this	O
change	O
of	O
marketing	O
focus	O
name	O
of	O
the	O
chip	O
family	O
name	O
was	O
changed	O
to	O
MCS-4	B-General_Concept
,	O
short	O
for	O
Micro	B-Architecture
Computer	I-Architecture
System	O
,	O
4-bit	O
.	O
</s>
<s>
As	O
Intel	O
was	O
now	O
successful	O
in	O
the	O
memory	O
market	O
,	O
they	O
were	O
concerned	O
the	O
4004	B-General_Concept
might	O
confuse	O
the	O
market	O
and	O
were	O
hesitant	O
to	O
advertise	O
it	O
.	O
</s>
<s>
Hoff	O
and	O
Mazor	O
were	O
also	O
concerned	O
that	O
the	O
design	O
's	O
limitations	O
would	O
make	O
it	O
less	O
interesting	O
to	O
users	O
who	O
were	O
accustomed	O
to	O
the	O
new	O
16-bit	O
minicomputers	B-Architecture
entering	O
the	O
market	O
at	O
that	O
time	O
.	O
</s>
<s>
The	O
4004	B-General_Concept
became	O
the	O
first	O
commercial	O
microprocessor	B-Architecture
available	O
for	O
general	O
use	O
.	O
</s>
<s>
In	O
December	O
1969	O
,	O
Intel	O
was	O
approached	O
by	O
Computer	B-General_Concept
Terminal	I-General_Concept
Corporation	O
(	O
CTC	O
)	O
to	O
produce	O
a	O
custom	O
bipolar	O
memory	O
chip	O
for	O
a	O
computer	B-General_Concept
terminal	I-General_Concept
they	O
were	O
designing	O
,	O
the	O
Datapoint	B-Device
2200	I-Device
.	O
</s>
<s>
Mazor	O
and	O
Hoff	O
considered	O
their	O
CPU	O
design	O
and	O
concluded	O
it	O
was	O
not	O
much	O
more	O
complicated	O
than	O
the	O
4004	B-General_Concept
,	O
and	O
that	O
it	O
could	O
be	O
implemented	O
as	O
a	O
single-chip	O
8-bit	O
CPU	O
.	O
</s>
<s>
A	O
few	O
weeks	O
before	O
they	O
hired	O
Faggin	O
,	O
in	O
March	O
1970	O
Intel	O
hired	O
Hal	O
Feeney	O
to	O
design	O
the	O
8008	B-General_Concept
,	O
at	O
that	O
time	O
called	O
1201	B-General_Concept
following	O
Intel	O
's	O
naming	O
convention	O
.	O
</s>
<s>
However	O
,	O
CTC	O
decided	O
to	O
initially	O
proceed	O
with	O
a	O
conventional	O
TTL	B-General_Concept
implementation	O
of	O
their	O
CPU	O
and	O
the	O
project	O
was	O
lowered	O
in	O
priority	O
.	O
</s>
<s>
In	O
January	O
1971	O
,	O
Feeney	O
was	O
reassigned	O
back	O
to	O
the	O
1201	B-General_Concept
under	O
Faggin	O
’s	O
supervision	O
and	O
production	O
chips	O
were	O
available	O
in	O
March	O
1972	O
.	O
</s>
<s>
The	O
tradeoffs	O
between	O
the	O
two	O
designs	O
were	O
that	O
with	O
the	O
4004	B-General_Concept
and	O
its	O
memory	O
and	O
I/O	B-General_Concept
chips	O
it	O
was	O
much	O
easier	O
to	O
build	O
a	O
complete	O
computer	O
system	O
while	O
the	O
8008	B-General_Concept
was	O
more	O
flexible	O
,	O
had	O
a	O
larger	O
16kB	O
address	B-General_Concept
space	I-General_Concept
,	O
and	O
offered	O
more	O
instructions	O
.	O
</s>
<s>
The	O
4004	B-General_Concept
was	O
used	O
where	O
the	O
cost	O
of	O
implementation	O
was	O
the	O
major	O
concern	O
,	O
and	O
became	O
widely	O
used	O
in	O
embedded	O
controllers	O
for	O
applications	O
like	O
microwave	O
ovens	O
or	O
traffic	O
lights	O
and	O
similar	O
roles	O
.	O
</s>
<s>
The	O
8008	B-General_Concept
instead	O
found	O
itself	O
mostly	O
used	O
in	O
user-programmable	O
applications	O
,	O
such	O
as	O
computer	B-General_Concept
terminals	I-General_Concept
,	O
microcomputers	B-Architecture
and	O
similar	O
roles	O
.	O
</s>
<s>
This	O
split	O
in	O
functionality	O
remains	O
to	O
this	O
day	O
,	O
with	O
the	O
former	O
being	O
known	O
as	O
a	O
microcontroller	B-Architecture
.	O
</s>
<s>
Three	O
other	O
CPU	B-Architecture
chip	I-Architecture
designs	O
were	O
produced	O
at	O
about	O
the	O
same	O
time	O
:	O
the	O
Four-Phase	O
Systems	O
AL1	O
,	O
done	O
in	O
1969	O
;	O
the	O
MP944	B-Device
,	O
completed	O
in	O
1970	O
and	O
used	O
in	O
the	O
F-14	O
Tomcat	O
fighter	O
jet	O
;	O
and	O
the	O
Texas	O
Instruments	O
TMS-0100	O
chip	O
,	O
announced	O
on	O
September	O
17	O
,	O
1971	O
.	O
</s>
<s>
The	O
MP944	B-Device
was	O
a	O
collection	O
of	O
six	O
chips	O
forming	O
a	O
single	O
processor	O
unit	O
.	O
</s>
<s>
It	O
is	O
the	O
precursor	O
of	O
the	O
TMS1000	B-Device
,	O
introduced	O
in	O
1974	O
,	O
which	O
is	O
considered	O
the	O
first	O
microcontroller	B-Architecture
—	O
i.e.	O
,	O
a	O
computer	O
on	O
a	O
chip	O
containing	O
not	O
only	O
the	O
CPU	O
,	O
but	O
also	O
ROM	O
,	O
RAM	B-Architecture
,	O
and	O
I/O	B-General_Concept
functions	O
.	O
</s>
<s>
The	O
MCS-4	B-General_Concept
family	O
of	O
four	O
chips	O
developed	O
by	O
Intel	O
,	O
of	O
which	O
the	O
4004	B-General_Concept
is	O
the	O
CPU	O
or	O
microprocessor	B-Architecture
,	O
was	O
far	O
more	O
versatile	O
and	O
powerful	O
than	O
the	O
single-chip	O
TMS1000	B-Device
,	O
allowing	O
the	O
creation	O
of	O
a	O
variety	O
of	O
small	O
computers	O
for	O
various	O
applications	O
.	O
</s>
<s>
Zilog	O
,	O
the	O
first	O
company	O
entirely	O
dedicated	O
to	O
microprocessors	B-Architecture
and	O
microcontrollers	B-Architecture
,	O
was	O
started	O
by	O
Federico	O
Faggin	O
and	O
Ralph	O
Ungermann	O
at	O
the	O
end	O
of	O
1974	O
.	O
</s>
<s>
If	O
the	O
word	O
“	O
microprocessor	B-Architecture
”	O
is	O
used	O
to	O
specify	O
a	O
general-purpose	O
CPU	O
integrated	O
into	O
a	O
single	O
chip	O
,	O
none	O
of	O
the	O
so-called	O
microprocessor	B-Architecture
chips	O
that	O
existed	O
prior	O
to	O
the	O
4004	B-General_Concept
deserve	O
that	O
name	O
.	O
</s>
<s>
The	O
4004	B-General_Concept
employs	O
an	O
10	O
μm	O
process	O
silicon-gate	O
enhancement-load	O
pMOS	B-Algorithm
technology	O
on	O
a	O
and	O
can	O
execute	O
approximately	O
instructions	O
per	O
second	O
;	O
a	O
single	O
instruction	O
cycle	O
is	O
The	O
original	O
clock	O
rate	O
design	O
goal	O
was	O
1MHz	O
,	O
the	O
same	O
as	O
the	O
IBM	O
1620	O
Model	O
I	O
.	O
</s>
<s>
The	O
Intel	B-General_Concept
4004	I-General_Concept
was	O
fabricated	O
using	O
masks	O
produced	O
by	O
physically	O
cutting	O
each	O
pattern	O
at	O
500x	O
magnification	O
on	O
a	O
large	O
sheet	O
of	O
Rubylith	O
photo-reducing	O
it	O
,	O
and	O
repeating	O
,	O
a	O
process	O
made	O
obsolete	O
by	O
current	O
computer	O
graphic	O
design	O
capabilities	O
.	O
</s>
<s>
For	O
the	O
purpose	O
of	O
testing	O
the	O
produced	O
chips	O
,	O
Faggin	O
developed	O
a	O
tester	O
for	O
silicon	B-Architecture
wafers	I-Architecture
of	O
MCS-4	B-General_Concept
family	O
that	O
was	O
itself	O
driven	O
by	O
4004	B-General_Concept
chip	O
.	O
</s>
<s>
The	O
tester	O
also	O
served	O
as	O
a	O
proof	O
for	O
the	O
management	O
that	O
Intel	B-General_Concept
4004	I-General_Concept
microprocessor	B-Architecture
could	O
be	O
used	O
not	O
only	O
in	O
calculator-like	O
products	O
,	O
but	O
also	O
for	O
control	O
applications	O
.	O
</s>
<s>
The	O
4004	B-General_Concept
includes	O
functions	O
for	O
direct	O
low-level	O
control	O
of	O
memory-chip	O
selection	O
and	O
I/O	B-General_Concept
,	O
which	O
are	O
not	O
normally	O
handled	O
by	O
the	O
microprocessor	B-Architecture
;	O
however	O
,	O
its	O
functionality	O
is	O
limited	O
in	O
that	O
it	O
cannot	O
execute	O
code	O
from	O
RAM	B-Architecture
and	O
is	O
limited	O
to	O
whatever	O
instructions	O
are	O
provided	O
in	O
ROM	O
(	O
or	O
an	O
independently	O
loaded	O
RAM	B-Architecture
working	O
as	O
ROM	O
—	O
in	O
either	O
case	O
,	O
the	O
processor	O
is	O
itself	O
unable	O
to	O
write	O
or	O
transfer	O
data	O
into	O
an	O
executable	O
memory	O
space	O
)	O
.	O
</s>
<s>
The	O
RAM	B-Architecture
and	O
ROM	O
parts	O
chips	O
also	O
unusual	O
in	O
their	O
integration	O
of	O
I/O	B-General_Concept
functions	O
together	O
with	O
their	O
primary	O
memory	O
function	O
.	O
</s>
<s>
this	O
partitioning	O
significantly	O
reduced	O
the	O
minimum	O
part	O
count	O
in	O
an	O
MCS-4	B-General_Concept
system	O
,	O
but	O
required	O
inclusion	O
of	O
a	O
certain	O
amount	O
of	O
processor-like	O
logic	O
on	O
the	O
memory	O
chips	O
themselves	O
to	O
accept	O
,	O
decode	O
and	O
execute	O
relatively	O
high-level	O
data-transfer	O
instructions	O
.	O
</s>
<s>
The	O
standard	O
arrangement	O
for	O
a	O
4004	B-General_Concept
system	O
is	O
anything	O
up	O
to	O
16	O
×	O
4001	O
ROM	O
chips	O
(	O
in	O
a	O
single	O
bank	O
)	O
and	O
16	O
×	O
4002	O
RAM	B-Architecture
chips	I-Architecture
(	O
in	O
four	O
banks	O
of	O
four	O
)	O
,	O
which	O
together	O
provide	O
the	O
4KB	O
program	O
storage	O
,	O
1024	O
+	O
256	O
nibbles	O
of	O
data/status	O
storage	O
,	O
plus	O
64	O
output	O
and	O
64	O
input/output	B-General_Concept
external	O
data/control	O
lines	O
(	O
which	O
can	O
themselves	O
be	O
used	O
to	O
operate	O
,	O
e.g.	O
</s>
<s>
Intel	O
's	O
MCS-4	B-General_Concept
documentation	O
,	O
however	O
,	O
claims	O
that	O
up	O
to	O
48	O
ROM	O
and	O
RAM	B-Architecture
chips	I-Architecture
(	O
providing	O
up	O
to	O
192	O
external	O
control	O
lines	O
)	O
"	O
in	O
any	O
combination	O
"	O
can	O
be	O
connected	O
to	O
the	O
4004	B-General_Concept
"	O
with	O
simple	O
gating	O
hardware	O
"	O
,	O
but	O
declines	O
to	O
give	O
any	O
further	O
detail	O
or	O
examples	O
of	O
how	O
this	O
would	O
actually	O
be	O
achieved	O
.	O
</s>
<s>
The	O
4004	B-General_Concept
had	O
this	O
maximum	O
clock	O
rating	O
upon	O
its	O
initial	O
1971	O
release	O
.	O
</s>
<s>
Contrary	O
to	O
Harvard	B-Architecture
architecture	I-Architecture
designs	O
,	O
however	O
,	O
which	O
use	O
separate	O
buses	O
,	O
the	O
4004	B-General_Concept
,	O
with	O
its	O
need	O
to	O
keep	O
pin	O
count	O
down	O
,	O
uses	O
a	O
single	O
multiplexed	B-Protocol
4-bit	O
bus	B-General_Concept
for	O
transferring	O
:	O
</s>
<s>
Able	O
to	O
directly	O
address	O
5120	O
bits	O
(	O
equivalent	O
to	O
640	O
bytes	B-Application
)	O
of	O
RAM	B-Architecture
,	O
stored	O
as	O
1280	O
4-bit	O
"	O
characters	O
"	O
and	O
organized	O
into	O
groups	O
representing	O
1024	O
"	O
data	O
"	O
and	O
256	O
"	O
status	O
"	O
characters	O
(	O
512	O
and	O
128	O
bytes	B-Application
)	O
.	O
</s>
<s>
bytes	B-Application
)	O
.	O
</s>
<s>
Instruction	B-General_Concept
set	I-General_Concept
contained	O
46	O
instructions	O
(	O
of	O
which	O
41	O
were	O
8	O
bits	O
wide	O
and	O
5	O
were	O
16	O
bits	O
wide	O
)	O
.	O
</s>
<s>
4001	O
:	O
256-byte	O
ROM	O
(	O
256	O
8-bit	O
program	O
instructions	O
)	O
and	O
one	O
built-in	O
4-bit	O
I/O	B-General_Concept
port	O
.	O
</s>
<s>
A	O
4001	O
ROM+	O
I/O	B-General_Concept
chip	O
cannot	O
be	O
used	O
in	O
a	O
system	O
along	O
with	O
a	O
4008/4009	O
pair	O
.	O
</s>
<s>
4002	O
:	O
40-byte	O
RAM	B-Architecture
(	O
80	O
4-bit	O
data	O
words	O
)	O
and	O
one	O
built-in	O
4-bit	O
output	O
port	O
;	O
the	O
RAM	B-Architecture
portion	O
of	O
the	O
chip	O
is	O
organized	O
into	O
4	O
"	O
registers	O
"	O
of	O
20	O
4-bit	O
words	O
:	O
</s>
<s>
16	O
data	O
words	O
(	O
used	O
for	O
mantissa	B-Algorithm
digits	O
in	O
the	O
original	O
calculator	O
design	O
)	O
,	O
accessed	O
in	O
a	O
relatively	O
standard	O
manner	O
,	O
</s>
<s>
4	O
status	O
words	O
(	O
used	O
for	O
exponent	O
digits	O
and	O
signs	O
in	O
the	O
original	O
calculator	O
design	O
)	O
,	O
accessed	O
using	O
I/O	B-General_Concept
type	O
commands	O
in	O
place	O
of	O
the	O
ROM	O
's	O
input	O
channel	O
.	O
</s>
<s>
4003	O
:	O
10-bit	O
parallel	O
output	O
shift	B-General_Concept
register	I-General_Concept
for	O
scanning	O
keyboards	O
,	O
displays	O
,	O
printers	O
,	O
etc	O
.	O
</s>
<s>
4008	O
:	O
8-bit	O
address	O
latch	O
for	O
access	O
to	O
standard	O
memory	O
chips	O
and	O
one	O
built-in	O
4-bit	O
chip-select	O
and	O
I/O	B-General_Concept
port	O
.	O
</s>
<s>
4009	O
:	O
program	O
and	O
I/O	B-General_Concept
access	O
converter	O
to	O
standard	O
memory	O
and	O
I/O	B-General_Concept
chips	O
.	O
</s>
<s>
The	O
minimum	O
system	O
specification	O
described	O
by	O
Intel	O
consists	O
of	O
a	O
4004	B-General_Concept
with	O
a	O
single	O
256-byte	O
4001	O
program	O
ROM	O
;	O
there	O
is	O
no	O
explicit	O
need	O
for	O
separate	O
RAM	B-Architecture
in	O
minimal-complexity	O
applications	O
thanks	O
to	O
the	O
4004	B-General_Concept
's	O
large	O
number	O
of	O
onboard	O
index	O
registers	O
,	O
which	O
represent	O
the	O
equivalent	O
of	O
16×	O
4-bit	O
or	O
8×	O
8-bit	O
characters	O
(	O
or	O
a	O
mixture	O
)	O
of	O
working	O
RAM	B-Architecture
,	O
nor	O
for	O
simple	O
interface	O
chips	O
thanks	O
to	O
the	O
ROM	O
's	O
built-in	O
I/O	B-General_Concept
lines	O
.	O
</s>
<s>
Numerous	O
versions	O
of	O
the	O
Intel	B-General_Concept
MCS-4	I-General_Concept
line	O
of	O
processors	O
were	O
produced	O
.	O
</s>
<s>
The	O
earliest	O
versions	O
,	O
marked	O
C	O
(	O
like	O
C4004	B-General_Concept
)	O
,	O
were	O
ceramic	O
and	O
used	O
a	O
zebra	O
pattern	O
of	O
white	O
and	O
gray	O
on	O
the	O
back	O
of	O
the	O
chips	O
,	O
often	O
called	O
"	O
grey	O
traces	O
"	O
.	O
</s>
<s>
Many	O
of	O
the	O
more	O
recent	O
versions	O
of	O
MCS-4	B-General_Concept
family	O
were	O
also	O
produced	O
with	O
plastic	O
(	O
P	O
)	O
.	O
</s>
<s>
The	O
first	O
commercial	O
product	O
to	O
use	O
a	O
microprocessor	B-Architecture
was	O
the	O
Busicom	O
calculator	O
141-PF	O
.	O
</s>
<s>
The	O
4004	B-General_Concept
was	O
also	O
used	O
in	O
the	O
first	O
microprocessor-controlled	O
pinball	B-Application
game	O
,	O
a	O
prototype	O
produced	O
by	O
Dave	O
Nutting	O
Associates	O
for	O
Bally	O
in	O
1974	O
.	O
</s>
<s>
In	O
1996	O
,	O
The	O
US	O
Patent	O
Office	O
officially	O
recognized	O
Mr.	O
Gary	O
W	O
.	O
Boone	O
and	O
his	O
employer	O
,	O
Texas	O
Instruments	O
,	O
as	O
the	O
inventors	O
of	O
the	O
single-chip	O
microcontroller	B-Architecture
,	O
overturning	O
the	O
patent	O
grant	O
to	O
Gilbert	O
P	O
.	O
Hyatt	O
in	O
1990	O
.	O
</s>
<s>
According	O
to	O
Nick	O
Tredennick	O
,	O
a	O
microprocessor	B-Architecture
designer	O
and	O
expert	O
witness	O
to	O
that	O
Boone/Hyatt	O
patent	O
case	O
:	O
</s>
<s>
A	O
popular	O
myth	O
has	O
it	O
that	O
Pioneer	O
10	O
,	O
the	O
first	O
spacecraft	O
to	O
leave	O
the	O
solar	O
system	O
,	O
used	O
an	O
Intel	B-General_Concept
4004	I-General_Concept
microprocessor	B-Architecture
.	O
</s>
<s>
According	O
to	O
Dr.	O
Larry	O
Lasher	O
of	O
Ames	O
Research	O
Center	O
,	O
the	O
Pioneer	O
team	O
did	O
evaluate	O
the	O
4004	B-General_Concept
,	O
but	O
decided	O
it	O
was	O
too	O
new	O
at	O
the	O
time	O
to	O
include	O
in	O
any	O
of	O
the	O
Pioneer	O
projects	O
.	O
</s>
<s>
Federico	O
Faggin	O
signed	O
the	O
4004	B-General_Concept
with	O
his	O
initials	O
because	O
he	O
knew	O
that	O
his	O
silicon	O
gate	O
design	O
embodied	O
"	O
the	O
essence	O
of	O
the	O
microprocessor	B-Architecture
"	O
.	O
</s>
<s>
On	O
November	O
15	O
,	O
2006	O
,	O
the	O
35th	O
anniversary	O
of	O
the	O
4004	B-General_Concept
,	O
Intel	O
celebrated	O
by	O
releasing	O
the	O
chip	O
's	O
schematics	B-Application
,	O
mask	O
works	O
,	O
and	O
user	O
manual	O
.	O
</s>
<s>
A	O
fully	O
functional	O
41	O
×	O
58cm	O
,	O
130×	O
scale	O
replica	O
of	O
the	O
Intel	B-General_Concept
4004	I-General_Concept
was	O
built	O
using	O
discrete	O
transistors	O
and	O
put	O
on	O
display	O
in	O
2006	O
at	O
the	O
Intel	O
Museum	O
in	O
Santa	O
Clara	O
,	O
California	O
.	O
</s>
<s>
On	O
October	O
15	O
,	O
2010	O
,	O
Faggin	O
,	O
Hoff	O
,	O
and	O
Mazor	O
were	O
awarded	O
the	O
National	O
Medal	O
of	O
Technology	O
and	O
Innovation	O
by	O
President	O
Barack	O
Obama	O
for	O
their	O
pioneering	O
work	O
on	O
the	O
4004	B-General_Concept
.	O
</s>
