<s>
The	O
instruction	B-General_Concept
unit	I-General_Concept
(	O
I-unit	B-General_Concept
or	O
IU	O
)	O
,	O
also	O
called	O
,	O
e.g.	O
,	O
instruction	O
fetch	O
unit	O
(	O
IFU	O
)	O
,	O
instruction	O
issue	O
unit	O
(	O
IIU	O
)	O
,	O
instruction	O
sequencing	O
unit	O
(	O
ISU	O
)	O
,	O
in	O
a	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
is	O
responsible	O
for	O
organizing	O
program	O
instructions	O
to	O
be	O
fetched	O
from	O
memory	O
,	O
and	O
executed	O
,	O
in	O
an	O
appropriate	O
order	O
,	O
and	O
for	O
forwarding	O
them	O
to	O
an	O
execution	B-General_Concept
unit	I-General_Concept
(	O
E-unit	O
or	O
EU	O
)	O
.	O
</s>
<s>
The	O
I-unit	B-General_Concept
may	O
also	O
do	O
,	O
e.g.	O
,	O
address	O
resolution	O
,	O
pre-fetching	O
,	O
prior	O
to	O
forwarding	O
an	O
instruction	O
.	O
</s>
<s>
It	O
is	O
a	O
part	O
of	O
the	O
control	B-General_Concept
unit	I-General_Concept
,	O
which	O
in	O
turn	O
is	O
part	O
of	O
the	O
CPU	O
.	O
</s>
<s>
In	O
the	O
simplest	O
style	O
of	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
the	O
instruction	B-General_Concept
cycle	I-General_Concept
is	O
very	O
rigid	O
,	O
and	O
runs	O
exactly	O
as	O
specified	O
by	O
the	O
programmer	B-Application
.	O
</s>
<s>
In	O
the	O
instruction	O
fetch	O
part	O
of	O
the	O
cycle	O
,	O
the	O
value	O
of	O
the	O
instruction	B-General_Concept
pointer	I-General_Concept
(	O
IP	O
)	O
register	O
is	O
the	O
address	O
of	O
the	O
next	B-General_Concept
instruction	I-General_Concept
to	O
be	O
fetched	O
.	O
</s>
<s>
This	O
value	O
is	O
placed	O
on	O
the	O
address	B-Architecture
bus	I-Architecture
and	O
sent	O
to	O
the	O
memory	B-General_Concept
unit	I-General_Concept
;	O
the	O
memory	B-General_Concept
unit	I-General_Concept
returns	O
the	O
instruction	O
at	O
that	O
address	O
,	O
and	O
it	O
is	O
latched	O
into	O
the	O
instruction	B-General_Concept
register	I-General_Concept
(	O
IR	O
)	O
;	O
and	O
the	O
value	O
of	O
the	O
IP	O
is	O
incremented	O
or	O
over-written	O
by	O
a	O
new	O
value	O
(	O
in	O
the	O
case	O
of	O
a	O
jump	O
or	O
branch	O
instruction	O
)	O
,	O
ready	O
for	O
the	O
next	B-General_Concept
instruction	I-General_Concept
cycle	O
.	O
</s>
<s>
This	O
becomes	O
a	O
lot	O
more	O
complicated	O
,	O
though	O
,	O
once	O
performance-enhancing	O
features	O
are	O
added	O
,	O
such	O
as	O
instruction	B-General_Concept
pipelining	I-General_Concept
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
and	O
even	O
just	O
the	O
introduction	O
of	O
a	O
simple	O
instruction	B-General_Concept
cache	I-General_Concept
.	O
</s>
