<s>
In	O
computing	O
,	O
the	O
instruction	B-General_Concept
register	I-General_Concept
(	O
IR	O
)	O
or	O
current	B-General_Concept
instruction	B-General_Concept
register	I-General_Concept
(	O
CIR	O
)	O
is	O
the	O
part	O
of	O
a	O
CPU	B-General_Concept
's	O
control	B-General_Concept
unit	I-General_Concept
that	O
holds	O
the	O
instruction	O
currently	O
being	O
executed	O
or	O
decoded	O
.	O
</s>
<s>
In	O
simple	O
processors	O
,	O
each	O
instruction	O
to	O
be	O
executed	O
is	O
loaded	O
into	O
the	O
instruction	B-General_Concept
register	I-General_Concept
,	O
which	O
holds	O
it	O
while	O
it	O
is	O
decoded	O
,	O
prepared	O
and	O
ultimately	O
executed	O
,	O
which	O
can	O
take	O
several	O
steps	O
.	O
</s>
<s>
Some	O
of	O
the	O
complicated	O
processors	O
use	O
a	O
pipeline	B-General_Concept
of	I-General_Concept
instruction	I-General_Concept
registers	I-General_Concept
where	O
each	O
stage	O
of	O
the	O
pipeline	O
does	O
part	O
of	O
the	O
decoding	O
,	O
preparation	O
or	O
execution	O
and	O
then	O
passes	O
it	O
to	O
the	O
next	O
stage	O
for	O
its	O
step	O
.	O
</s>
<s>
Decoding	O
the	O
op-code	B-Language
in	O
the	O
instruction	B-General_Concept
register	I-General_Concept
includes	O
determining	O
the	O
instruction	O
,	O
determining	O
where	O
its	O
operands	O
are	O
in	O
memory	O
,	O
retrieving	O
the	O
operands	O
from	O
memory	O
,	O
allocating	O
processor	O
resources	O
to	O
execute	O
the	O
command	O
(	O
in	O
super	B-General_Concept
scalar	I-General_Concept
processors	O
)	O
,	O
etc	O
.	O
</s>
<s>
In	O
the	O
instruction	B-General_Concept
cycle	I-General_Concept
,	O
the	O
instruction	O
is	O
loaded	O
into	O
the	O
instruction	B-General_Concept
register	I-General_Concept
after	O
the	O
processor	O
fetches	O
it	O
from	O
the	O
memory	O
location	O
pointed	O
to	O
by	O
the	O
program	B-General_Concept
counter	I-General_Concept
.	O
</s>
