<s>
In	O
the	O
fourth	O
clock	O
cycle	O
(	O
the	O
green	O
column	O
)	O
,	O
the	O
earliest	O
instruction	O
is	O
in	O
MEM	O
stage	O
,	O
and	O
the	O
latest	O
instruction	O
has	O
not	O
yet	O
entered	O
the	O
pipeline	B-General_Concept
.	O
</s>
<s>
In	O
computer	O
engineering	O
,	O
instruction	B-General_Concept
pipelining	I-General_Concept
is	O
a	O
technique	O
for	O
implementing	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
within	O
a	O
single	O
processor	O
.	O
</s>
<s>
Pipelining	B-General_Concept
attempts	O
to	O
keep	O
every	O
part	O
of	O
the	O
processor	O
busy	O
with	O
some	O
instruction	O
by	O
dividing	O
incoming	O
instructions	B-Language
into	O
a	O
series	O
of	O
sequential	O
steps	O
(	O
the	O
eponymous	O
"	O
pipeline	B-General_Concept
"	O
)	O
performed	O
by	O
different	O
processor	O
units	O
with	O
different	O
parts	O
of	O
instructions	B-Language
processed	O
in	O
parallel	O
.	O
</s>
<s>
In	O
a	O
pipelined	O
computer	O
,	O
instructions	B-Language
flow	O
through	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	B-Device
)	O
in	O
stages	O
.	O
</s>
<s>
For	O
example	O
,	O
it	O
might	O
have	O
one	O
stage	O
for	O
each	O
step	O
of	O
the	O
von	B-Architecture
Neumann	I-Architecture
cycle	I-Architecture
:	O
Fetch	O
the	O
instruction	O
,	O
fetch	O
the	O
operands	O
,	O
do	O
the	O
instruction	O
,	O
write	O
the	O
results	O
.	O
</s>
<s>
A	O
pipelined	O
computer	O
usually	O
has	O
"	O
pipeline	B-General_Concept
registers	O
"	O
after	O
each	O
stage	O
.	O
</s>
<s>
This	O
arrangement	O
lets	O
the	O
CPU	B-Device
complete	O
an	O
instruction	O
on	O
each	O
clock	O
cycle	O
.	O
</s>
<s>
This	O
allows	O
more	O
CPU	B-Device
throughput	O
than	O
a	O
multicycle	O
computer	O
at	O
a	O
given	O
clock	O
rate	O
,	O
but	O
may	O
increase	O
latency	O
due	O
to	O
the	O
added	O
overhead	O
of	O
the	O
pipelining	B-General_Concept
process	O
itself	O
.	O
</s>
<s>
Also	O
,	O
even	O
though	O
the	O
electronic	O
logic	O
has	O
a	O
fixed	O
maximum	O
speed	O
,	O
a	O
pipelined	O
computer	O
can	O
be	O
made	O
faster	O
or	O
slower	O
by	O
varying	O
the	O
number	O
of	O
stages	O
in	O
the	O
pipeline	B-General_Concept
.	O
</s>
<s>
At	O
each	O
instant	O
,	O
an	O
instruction	O
is	O
in	O
only	O
one	O
pipeline	B-General_Concept
stage	O
,	O
and	O
on	O
average	O
,	O
a	O
pipeline	B-General_Concept
stage	O
is	O
less	O
costly	O
than	O
a	O
multicycle	O
computer	O
.	O
</s>
<s>
Out	O
of	O
order	O
CPUs	B-Device
can	O
usually	O
do	O
more	O
instructions	B-Language
per	O
second	O
because	O
they	O
can	O
do	O
several	O
instructions	B-Language
at	O
once	O
.	O
</s>
<s>
The	O
instruction	O
data	O
is	O
usually	O
passed	O
in	O
pipeline	B-General_Concept
registers	O
from	O
one	O
stage	O
to	O
the	O
next	O
,	O
with	O
a	O
somewhat	O
separated	O
piece	O
of	O
control	O
logic	O
for	O
each	O
stage	O
.	O
</s>
<s>
The	O
control	O
unit	O
also	O
assures	O
that	O
the	O
instruction	O
in	O
each	O
stage	O
does	O
not	O
harm	O
the	O
operation	O
of	O
instructions	B-Language
in	O
other	O
stages	O
.	O
</s>
<s>
It	O
is	O
then	O
working	O
on	O
all	O
of	O
those	O
instructions	B-Language
at	O
the	O
same	O
time	O
.	O
</s>
<s>
But	O
when	O
a	O
program	O
switches	O
to	O
a	O
different	O
sequence	O
of	O
instructions	B-Language
,	O
the	O
pipeline	B-General_Concept
sometimes	O
must	O
discard	O
the	O
data	O
in	O
process	O
and	O
restart	O
.	O
</s>
<s>
This	O
is	O
called	O
a	O
"	O
stall.	O
"	O
</s>
<s>
The	O
1956	O
–	O
61	O
IBM	B-Device
Stretch	I-Device
project	O
proposed	O
the	O
terms	O
Fetch	O
,	O
Decode	O
,	O
and	O
Execute	O
that	O
have	O
become	O
common	O
.	O
</s>
<s>
The	O
classic	B-General_Concept
RISC	I-General_Concept
pipeline	I-General_Concept
comprises	O
:	O
</s>
<s>
The	O
Atmel	B-Architecture
AVR	I-Architecture
and	O
the	O
PIC	B-Architecture
microcontroller	I-Architecture
each	O
have	O
a	O
two-stage	O
pipeline	B-General_Concept
.	O
</s>
<s>
Many	O
designs	O
include	O
pipelines	B-General_Concept
as	O
long	O
as	O
7	O
,	O
10	O
and	O
even	O
20	O
stages	O
(	O
as	O
in	O
the	O
Intel	B-General_Concept
Pentium	I-General_Concept
4	I-General_Concept
)	O
.	O
</s>
<s>
The	O
later	O
"	O
Prescott	O
"	O
and	O
"	O
Cedar	O
Mill	O
"	O
NetBurst	B-Device
cores	O
from	O
Intel	O
,	O
used	O
in	O
the	O
last	O
Pentium4	B-General_Concept
models	O
and	O
their	O
Pentium	B-Device
D	I-Device
and	O
Xeon	B-Device
derivatives	O
,	O
have	O
a	O
long	O
31-stage	O
pipeline	B-General_Concept
.	O
</s>
<s>
The	O
Xelerated	O
X10q	O
Network	O
Processor	O
has	O
a	O
pipeline	B-General_Concept
more	O
than	O
a	O
thousand	O
stages	O
long	O
,	O
although	O
in	O
this	O
case	O
200	O
of	O
these	O
stages	O
represent	O
independent	O
CPUs	B-Device
with	O
individually	O
programmed	O
instructions	B-Language
.	O
</s>
<s>
As	O
the	O
pipeline	B-General_Concept
is	O
made	O
"	O
deeper	O
"	O
(	O
with	O
a	O
greater	O
number	O
of	O
dependent	O
steps	O
)	O
,	O
a	O
given	O
step	O
can	O
be	O
implemented	O
with	O
simpler	O
circuitry	O
,	O
which	O
may	O
let	O
the	O
processor	O
clock	O
run	O
faster	O
.	O
</s>
<s>
Such	O
pipelines	B-General_Concept
may	O
be	O
called	O
superpipelines	O
.	O
</s>
<s>
Thus	O
,	O
if	O
some	O
instructions	B-Language
or	O
conditions	O
require	O
delays	O
that	O
inhibit	O
fetching	O
new	O
instructions	B-Language
,	O
the	O
processor	O
is	O
not	O
fully	O
pipelined	O
.	O
</s>
<s>
Seminal	O
uses	O
of	O
pipelining	B-General_Concept
were	O
in	O
the	O
ILLIAC	B-Device
II	I-Device
project	O
and	O
the	O
IBM	B-Device
Stretch	I-Device
project	O
,	O
though	O
a	O
simple	O
version	O
was	O
used	O
earlier	O
in	O
the	O
Z1	B-Device
in	O
1939	O
and	O
the	O
Z3	B-Device
in	O
1941	O
.	O
</s>
<s>
Pipelining	B-General_Concept
began	O
in	O
earnest	O
in	O
the	O
late	O
1970s	O
in	O
supercomputers	B-Architecture
such	O
as	O
vector	O
processors	O
and	O
array	O
processors	O
.	O
</s>
<s>
One	O
of	O
the	O
early	O
supercomputers	B-Architecture
was	O
the	O
Cyber	O
series	O
built	O
by	O
Control	O
Data	O
Corporation	O
.	O
</s>
<s>
Cray	O
developed	O
the	O
XMP	O
line	O
of	O
supercomputers	B-Architecture
,	O
using	O
pipelining	B-General_Concept
for	O
both	O
multiply	O
and	O
add/subtract	O
functions	O
.	O
</s>
<s>
By	O
the	O
mid-1980s	O
,	O
pipelining	B-General_Concept
was	O
used	O
by	O
many	O
different	O
companies	O
around	O
the	O
world	O
.	O
</s>
<s>
Pipelining	B-General_Concept
was	O
not	O
limited	O
to	O
supercomputers	B-Architecture
.	O
</s>
<s>
In	O
1976	O
,	O
the	O
Amdahl	O
Corporation	O
's	O
470	O
series	O
general	O
purpose	O
mainframe	O
had	O
a	O
7-step	O
pipeline	B-General_Concept
,	O
and	O
a	O
patented	O
branch	B-General_Concept
prediction	I-General_Concept
circuit	O
.	O
</s>
<s>
The	O
model	O
of	O
sequential	O
execution	O
assumes	O
that	O
each	O
instruction	O
completes	O
before	O
the	O
next	O
one	O
begins	O
;	O
this	O
assumption	O
is	O
not	O
true	O
on	O
a	O
pipelined	B-General_Concept
processor	I-General_Concept
.	O
</s>
<s>
A	O
situation	O
where	O
the	O
expected	O
result	O
is	O
problematic	O
is	O
known	O
as	O
a	O
hazard	B-General_Concept
.	O
</s>
<s>
Imagine	O
the	O
following	O
two	O
register	O
instructions	B-Language
to	O
a	O
hypothetical	O
processor	O
:	O
</s>
<s>
If	O
the	O
processor	O
has	O
the	O
5	O
steps	O
listed	O
in	O
the	O
initial	O
illustration	O
(	O
the	O
'	O
Basic	B-General_Concept
five-stage	I-General_Concept
pipeline	I-General_Concept
 '	O
at	O
the	O
start	O
of	O
the	O
article	O
)	O
,	O
instruction	O
1	O
would	O
be	O
fetched	O
at	O
time	O
t1	O
and	O
its	O
execution	O
would	O
be	O
complete	O
at	O
t5	O
.	O
</s>
<s>
The	O
above	O
code	O
invokes	O
a	O
hazard	B-General_Concept
.	O
</s>
<s>
Writing	O
computer	O
programs	O
in	O
a	O
compiled	B-Language
language	O
might	O
not	O
raise	O
these	O
concerns	O
,	O
as	O
the	O
compiler	B-Language
could	O
be	O
designed	O
to	O
generate	O
machine	B-Language
code	I-Language
that	O
avoids	O
hazards	B-General_Concept
.	O
</s>
<s>
In	O
some	O
early	O
DSP	O
and	O
RISC	O
processors	O
,	O
the	O
documentation	O
advises	O
programmers	O
to	O
avoid	O
such	O
dependencies	O
in	O
adjacent	O
and	O
nearly	O
adjacent	O
instructions	B-Language
(	O
called	O
delay	B-General_Concept
slots	I-General_Concept
)	O
,	O
or	O
declares	O
that	O
the	O
second	O
instruction	O
uses	O
an	O
old	O
value	O
rather	O
than	O
the	O
desired	O
value	O
(	O
in	O
the	O
example	O
above	O
,	O
the	O
processor	O
might	O
counter-intuitively	O
copy	O
the	O
unincremented	O
value	O
)	O
,	O
or	O
declares	O
that	O
the	O
value	O
it	O
uses	O
is	O
undefined	O
.	O
</s>
<s>
The	O
programmer	O
may	O
have	O
unrelated	O
work	O
that	O
the	O
processor	O
can	O
do	O
in	O
the	O
meantime	O
;	O
or	O
,	O
to	O
ensure	O
correct	O
results	O
,	O
the	O
programmer	O
may	O
insert	O
NOPs	B-Language
into	O
the	O
code	O
,	O
partly	O
negating	O
the	O
advantages	O
of	O
pipelining	B-General_Concept
.	O
</s>
<s>
Pipelined	B-General_Concept
processors	I-General_Concept
commonly	O
use	O
three	O
techniques	O
to	O
work	O
as	O
expected	O
when	O
the	O
programmer	O
assumes	O
that	O
each	O
instruction	O
completes	O
before	O
the	O
next	O
one	O
begins	O
:	O
</s>
<s>
The	O
pipeline	B-General_Concept
could	O
stall	B-General_Concept
,	O
or	O
cease	O
scheduling	O
new	O
instructions	B-Language
until	O
the	O
required	O
values	O
are	O
available	O
.	O
</s>
<s>
This	O
results	O
in	O
empty	O
slots	O
in	O
the	O
pipeline	B-General_Concept
,	O
or	O
bubbles	B-General_Concept
,	O
in	O
which	O
no	O
work	O
is	O
performed	O
.	O
</s>
<s>
An	O
additional	O
data	O
path	O
can	O
be	O
added	O
that	O
routes	O
a	O
computed	O
value	O
to	O
a	O
future	O
instruction	O
elsewhere	O
in	O
the	O
pipeline	B-General_Concept
before	O
the	O
instruction	O
that	O
produced	O
it	O
has	O
been	O
fully	O
retired	O
,	O
a	O
process	O
called	O
operand	B-General_Concept
forwarding	I-General_Concept
.	O
</s>
<s>
The	O
processor	O
can	O
locate	O
other	O
instructions	B-Language
which	O
are	O
not	O
dependent	O
on	O
the	O
current	O
ones	O
and	O
which	O
can	O
be	O
immediately	O
executed	O
without	O
hazards	B-General_Concept
,	O
an	O
optimization	O
known	O
as	O
out-of-order	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
A	O
branch	O
out	O
of	O
the	O
normal	O
instruction	O
sequence	O
often	O
involves	O
a	O
hazard	B-General_Concept
.	O
</s>
<s>
Unless	O
the	O
processor	O
can	O
give	O
effect	O
to	O
the	O
branch	O
in	O
a	O
single	O
time	O
cycle	O
,	O
the	O
pipeline	B-General_Concept
will	O
continue	O
fetching	O
instructions	B-Language
sequentially	O
.	O
</s>
<s>
Such	O
instructions	B-Language
cannot	O
be	O
allowed	O
to	O
take	O
effect	O
because	O
the	O
programmer	O
has	O
diverted	O
control	O
to	O
another	O
part	O
of	O
the	O
program	O
.	O
</s>
<s>
Various	O
processors	O
may	O
stall	B-General_Concept
,	O
may	O
attempt	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
and	O
may	O
be	O
able	O
to	O
begin	O
to	O
execute	O
two	O
different	O
program	O
sequences	O
(	O
eager	O
execution	O
)	O
,	O
each	O
assuming	O
the	O
branch	O
is	O
or	O
is	O
not	O
taken	O
,	O
discarding	O
all	O
work	O
that	O
pertains	O
to	O
the	O
incorrect	O
guess	O
.	O
</s>
<s>
A	O
processor	O
with	O
an	O
implementation	O
of	O
branch	B-General_Concept
prediction	I-General_Concept
that	O
usually	O
makes	O
correct	O
predictions	O
can	O
minimize	O
the	O
performance	O
penalty	O
from	O
branching	O
.	O
</s>
<s>
However	O
,	O
if	O
branches	O
are	O
predicted	O
poorly	O
,	O
it	O
may	O
create	O
more	O
work	O
for	O
the	O
processor	O
,	O
such	O
as	O
flushing	O
from	O
the	O
pipeline	B-General_Concept
the	O
incorrect	O
code	O
path	O
that	O
has	O
begun	O
execution	O
before	O
resuming	O
execution	O
at	O
the	O
correct	O
location	O
.	O
</s>
<s>
Programs	O
written	O
for	O
a	O
pipelined	B-General_Concept
processor	I-General_Concept
deliberately	O
avoid	O
branching	O
to	O
minimize	O
possible	O
loss	O
of	O
speed	O
.	O
</s>
<s>
Using	O
programs	O
such	O
as	O
gcov	B-Application
to	O
analyze	O
code	B-Application
coverage	I-Application
lets	O
the	O
programmer	O
measure	O
how	O
often	O
particular	O
branches	O
are	O
actually	O
executed	O
and	O
gain	O
insight	O
with	O
which	O
to	O
optimize	O
the	O
code	O
.	O
</s>
<s>
The	O
technique	O
of	O
self-modifying	B-Application
code	I-Application
can	O
be	O
problematic	O
on	O
a	O
pipelined	B-General_Concept
processor	I-General_Concept
.	O
</s>
<s>
In	O
this	O
technique	O
,	O
one	O
of	O
the	O
effects	O
of	O
a	O
program	O
is	O
to	O
modify	O
its	O
own	O
upcoming	O
instructions	B-Language
.	O
</s>
<s>
If	O
the	O
processor	O
has	O
an	O
instruction	O
cache	O
,	O
the	O
original	O
instruction	O
may	O
already	O
have	O
been	O
copied	O
into	O
a	O
prefetch	B-General_Concept
input	I-General_Concept
queue	I-General_Concept
and	O
the	O
modification	O
will	O
not	O
take	O
effect	O
.	O
</s>
<s>
Some	O
processors	O
such	O
as	O
the	O
Zilog	B-Device
Z280	I-Device
can	O
configure	O
their	O
on-chip	O
cache	O
memories	O
for	O
data-only	O
fetches	O
,	O
or	O
as	O
part	O
of	O
their	O
ordinary	O
memory	O
address	O
space	O
,	O
and	O
avoid	O
such	O
difficulties	O
with	O
self-modifying	O
instructions	B-Language
.	O
</s>
<s>
An	O
instruction	O
may	O
be	O
uninterruptible	O
to	O
ensure	O
its	O
atomicity	B-General_Concept
,	O
such	O
as	O
when	O
it	O
swaps	O
two	O
items	O
.	O
</s>
<s>
A	O
sequential	O
processor	O
permits	O
interrupts	B-Application
between	O
instructions	B-Language
,	O
but	O
a	O
pipelining	B-General_Concept
processor	O
overlaps	O
instructions	B-Language
,	O
so	O
executing	O
an	O
uninterruptible	O
instruction	O
renders	O
portions	O
of	O
ordinary	O
instructions	B-Language
uninterruptible	O
too	O
.	O
</s>
<s>
The	O
Cyrix	B-Error_Name
coma	I-Error_Name
bug	I-Error_Name
would	O
hang	B-General_Concept
a	O
single-core	O
system	O
using	O
an	O
infinite	O
loop	O
in	O
which	O
an	O
uninterruptible	O
instruction	O
was	O
always	O
in	O
the	O
pipeline	B-General_Concept
.	O
</s>
<s>
Pipelining	B-General_Concept
keeps	O
all	O
portions	O
of	O
the	O
processor	O
occupied	O
and	O
increases	O
the	O
amount	O
of	O
useful	O
work	O
the	O
processor	O
can	O
do	O
in	O
a	O
given	O
time	O
.	O
</s>
<s>
Pipelining	B-General_Concept
typically	O
reduces	O
the	O
processor	O
's	O
cycle	O
time	O
and	O
increases	O
the	O
throughput	O
of	O
instructions	B-Language
.	O
</s>
<s>
The	O
speed	O
advantage	O
is	O
diminished	O
to	O
the	O
extent	O
that	O
execution	O
encounters	O
hazards	B-General_Concept
that	O
require	O
execution	O
to	O
slow	O
below	O
its	O
ideal	O
rate	O
.	O
</s>
<s>
The	O
start	O
of	O
the	O
next	O
instruction	O
is	O
delayed	O
not	O
based	O
on	O
hazards	B-General_Concept
but	O
unconditionally	O
.	O
</s>
<s>
A	O
pipelined	B-General_Concept
processor	I-General_Concept
's	O
need	O
to	O
organize	O
all	O
its	O
work	O
into	O
modular	O
steps	O
may	O
require	O
the	O
duplication	O
of	O
registers	O
,	O
which	O
increases	O
the	O
latency	O
of	O
some	O
instructions	B-Language
.	O
</s>
<s>
By	O
making	O
each	O
dependent	O
step	O
simpler	O
,	O
pipelining	B-General_Concept
can	O
enable	O
complex	O
operations	O
more	O
economically	O
than	O
adding	O
complex	O
circuitry	O
,	O
such	O
as	O
for	O
numerical	O
calculations	O
.	O
</s>
<s>
However	O
,	O
a	O
processor	O
that	O
declines	O
to	O
pursue	O
increased	O
speed	O
with	O
pipelining	B-General_Concept
may	O
be	O
simpler	O
and	O
cheaper	O
to	O
manufacture	O
.	O
</s>
<s>
Compared	O
to	O
environments	O
where	O
the	O
programmer	O
needs	O
to	O
avoid	O
or	O
work	O
around	O
hazards	B-General_Concept
,	O
use	O
of	O
a	O
non-pipelined	O
processor	O
may	O
make	O
it	O
easier	O
to	O
program	O
and	O
to	O
train	O
programmers	O
.	O
</s>
<s>
The	O
non-pipelined	O
processor	O
also	O
makes	O
it	O
easier	O
to	O
predict	O
the	O
exact	O
timing	O
of	O
a	O
given	O
sequence	O
of	O
instructions	B-Language
.	O
</s>
<s>
To	O
the	O
right	O
is	O
a	O
generic	O
pipeline	B-General_Concept
with	O
four	O
stages	O
:	O
fetch	O
,	O
decode	O
,	O
execute	O
and	O
write-back	O
.	O
</s>
<s>
The	O
top	O
gray	O
box	O
is	O
the	O
list	O
of	O
instructions	B-Language
waiting	O
to	O
be	O
executed	O
,	O
the	O
bottom	O
gray	O
box	O
is	O
the	O
list	O
of	O
instructions	B-Language
that	O
have	O
had	O
their	O
execution	O
completed	O
,	O
and	O
the	O
middle	O
white	O
box	O
is	O
the	O
pipeline	B-General_Concept
.	O
</s>
<s>
A	O
pipelined	B-General_Concept
processor	I-General_Concept
may	O
deal	O
with	O
hazards	B-General_Concept
by	O
stalling	O
and	O
creating	O
a	O
bubble	B-General_Concept
in	O
the	O
pipeline	B-General_Concept
,	O
resulting	O
in	O
one	O
or	O
more	O
cycles	O
in	O
which	O
nothing	O
useful	O
happens	O
.	O
</s>
<s>
Because	O
of	O
the	O
bubble	B-General_Concept
(	O
the	O
blue	O
ovals	O
in	O
the	O
illustration	O
)	O
,	O
the	O
processor	O
's	O
Decode	O
circuitry	O
is	O
idle	O
during	O
cycle	O
3	O
.	O
</s>
<s>
When	O
the	O
bubble	B-General_Concept
moves	O
out	O
of	O
the	O
pipeline	B-General_Concept
(	O
at	O
cycle	O
6	O
)	O
,	O
normal	O
execution	O
resumes	O
.	O
</s>
<s>
It	O
will	O
take	O
8	O
cycles	O
(	O
cycle	O
1	O
through	O
8	O
)	O
rather	O
than	O
7	O
to	O
completely	O
execute	O
the	O
four	O
instructions	B-Language
shown	O
in	O
colors	O
.	O
</s>
