<s>
The	O
instruction	B-General_Concept
cycle	I-General_Concept
(	O
also	O
known	O
as	O
the	O
fetch	O
–	O
decode	O
–	O
execute	B-General_Concept
cycle	I-General_Concept
,	O
or	O
simply	O
the	O
fetch-execute	B-General_Concept
cycle	I-General_Concept
)	O
is	O
the	O
cycle	O
that	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	B-Device
)	O
follows	O
from	O
boot-up	B-Operating_System
until	O
the	O
computer	O
has	O
shut	O
down	O
in	O
order	O
to	O
process	O
instructions	O
.	O
</s>
<s>
In	O
simpler	O
CPUs	B-Device
,	O
the	O
instruction	B-General_Concept
cycle	I-General_Concept
is	O
executed	O
sequentially	O
,	O
each	O
instruction	O
being	O
processed	O
before	O
the	O
next	O
one	O
is	O
started	O
.	O
</s>
<s>
In	O
most	O
modern	O
CPUs	B-Device
,	O
the	O
instruction	B-General_Concept
cycles	I-General_Concept
are	O
instead	O
executed	O
concurrently	B-Architecture
,	O
and	O
often	O
in	O
parallel	B-Operating_System
,	O
through	O
an	O
instruction	B-General_Concept
pipeline	I-General_Concept
:	O
the	O
next	B-General_Concept
instruction	I-General_Concept
starts	O
being	O
processed	O
before	O
the	O
previous	O
instruction	O
has	O
finished	O
,	O
which	O
is	O
possible	O
because	O
the	O
cycle	O
is	O
broken	O
up	O
into	O
separate	O
steps	O
.	O
</s>
<s>
The	O
program	B-General_Concept
counter	I-General_Concept
(	O
PC	O
)	O
is	O
a	O
special	O
register	B-General_Concept
that	O
holds	O
the	O
memory	O
address	O
of	O
the	O
next	B-General_Concept
instruction	I-General_Concept
to	O
be	O
executed	O
.	O
</s>
<s>
During	O
the	O
fetch	O
stage	O
,	O
the	O
address	O
stored	O
in	O
the	O
PC	O
is	O
copied	O
into	O
the	O
memory	B-General_Concept
address	I-General_Concept
register	I-General_Concept
(	O
MAR	O
)	O
and	O
then	O
the	O
PC	O
is	O
incremented	O
in	O
order	O
to	O
"	O
point	O
"	O
to	O
the	O
memory	O
address	O
of	O
the	O
next	B-General_Concept
instruction	I-General_Concept
to	O
be	O
executed	O
.	O
</s>
<s>
The	O
CPU	B-Device
then	O
takes	O
the	O
instruction	O
at	O
the	O
memory	O
address	O
described	O
by	O
the	O
MAR	O
and	O
copies	O
it	O
into	O
the	O
memory	B-General_Concept
data	I-General_Concept
register	I-General_Concept
(	O
MDR	O
)	O
.	O
</s>
<s>
The	O
MDR	O
also	O
acts	O
as	O
a	O
two-way	O
register	B-General_Concept
that	O
holds	O
data	O
fetched	O
from	O
memory	O
or	O
data	O
waiting	O
to	O
be	O
stored	O
in	O
memory	O
(	O
it	O
is	O
also	O
known	O
as	O
the	O
memory	B-General_Concept
buffer	I-General_Concept
register	I-General_Concept
(	O
MBR	O
)	O
because	O
of	O
this	O
)	O
.	O
</s>
<s>
Eventually	O
,	O
the	O
instruction	O
in	O
the	O
MDR	O
is	O
copied	O
into	O
the	O
current	B-General_Concept
instruction	I-General_Concept
register	I-General_Concept
(	O
CIR	O
)	O
which	O
acts	O
as	O
a	O
temporary	O
holding	O
ground	O
for	O
the	O
instruction	O
that	O
has	O
just	O
been	O
fetched	O
from	O
memory	O
.	O
</s>
<s>
During	O
the	O
decode	O
stage	O
,	O
the	O
control	B-General_Concept
unit	I-General_Concept
(	O
CU	O
)	O
will	O
decode	O
the	O
instruction	O
in	O
the	O
CIR	O
.	O
</s>
<s>
The	O
CU	O
then	O
sends	O
signals	O
to	O
other	O
components	O
within	O
the	O
CPU	B-Device
,	O
such	O
as	O
the	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
and	O
the	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
.	O
</s>
<s>
The	O
FPU	O
is	O
reserved	O
for	O
performing	O
floating-point	B-Algorithm
operations	I-Algorithm
.	O
</s>
<s>
Each	O
computer	O
's	O
CPU	B-Device
can	O
have	O
different	O
cycles	O
based	O
on	O
different	O
instruction	O
sets	O
,	O
but	O
will	O
be	O
similar	O
to	O
the	O
following	O
cycle	O
:	O
</s>
<s>
Fetch	O
stage	O
:	O
The	O
next	B-General_Concept
instruction	I-General_Concept
is	O
fetched	O
from	O
the	O
memory	O
address	O
that	O
is	O
currently	O
stored	O
in	O
the	O
program	B-General_Concept
counter	I-General_Concept
and	O
stored	O
into	O
the	O
instruction	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
At	O
the	O
end	O
of	O
the	O
fetch	O
operation	O
,	O
the	O
PC	O
points	O
to	O
the	O
next	B-General_Concept
instruction	I-General_Concept
that	O
will	O
be	O
read	O
at	O
the	O
next	O
cycle	O
.	O
</s>
<s>
Decode	O
stage	O
:	O
During	O
this	O
stage	O
,	O
the	O
encoded	O
instruction	O
presented	O
in	O
the	O
instruction	B-General_Concept
register	I-General_Concept
is	O
interpreted	O
by	O
the	O
decoder	O
.	O
</s>
<s>
Read	O
the	O
effective	B-Language
address	I-Language
:	O
In	O
the	O
case	O
of	O
a	O
memory	O
instruction	O
(	O
direct	O
or	O
indirect	O
)	O
,	O
the	O
execution	O
phase	O
will	O
be	O
during	O
the	O
next	O
clock	O
pulse	O
.	O
</s>
<s>
If	O
the	O
instruction	O
has	O
an	O
indirect	B-Language
address	I-Language
,	O
the	O
effective	B-Language
address	I-Language
is	O
read	O
from	O
main	O
memory	O
,	O
and	O
any	O
required	O
data	O
is	O
fetched	O
from	O
main	O
memory	O
to	O
be	O
processed	O
and	O
then	O
placed	O
into	O
data	O
registers	O
(	O
clock	O
pulse	O
:	O
T3	O
)	O
.	O
</s>
<s>
If	O
this	O
is	O
an	O
I/O	O
instruction	O
or	O
a	O
register	B-General_Concept
instruction	O
,	O
the	O
operation	O
is	O
performed	O
during	O
the	O
clock	O
pulse	O
.	O
</s>
<s>
Execute	O
stage	O
:	O
The	O
control	B-General_Concept
unit	I-General_Concept
of	O
the	O
CPU	B-Device
passes	O
the	O
decoded	O
information	O
as	O
a	O
sequence	O
of	O
control	O
signals	O
to	O
the	O
relevant	O
functional	O
units	O
of	O
the	O
CPU	B-Device
to	O
perform	O
the	O
actions	O
required	O
by	O
the	O
instruction	O
,	O
such	O
as	O
reading	O
values	O
from	O
registers	O
,	O
passing	O
them	O
to	O
the	O
ALU	O
to	O
perform	O
mathematical	O
or	O
logic	O
functions	O
on	O
them	O
,	O
and	O
writing	O
the	O
result	O
back	O
to	O
a	O
register	B-General_Concept
.	O
</s>
<s>
Based	O
on	O
the	O
feedback	O
from	O
the	O
ALU	O
,	O
the	O
PC	O
may	O
be	O
updated	O
to	O
a	O
different	O
address	O
from	O
which	O
the	O
next	B-General_Concept
instruction	I-General_Concept
will	O
be	O
fetched	O
.	O
</s>
<s>
In	O
addition	O
,	O
on	O
most	O
processors	O
interrupts	B-Application
can	O
occur	O
.	O
</s>
<s>
This	O
will	O
cause	O
the	O
CPU	B-Device
to	O
jump	O
to	O
an	O
interrupt	B-Application
service	O
routine	O
,	O
execute	O
that	O
and	O
then	O
return	O
.	O
</s>
<s>
In	O
some	O
cases	O
an	O
instruction	O
can	O
be	O
interrupted	O
in	O
the	O
middle	O
,	O
the	O
instruction	O
will	O
have	O
no	O
effect	O
,	O
but	O
will	O
be	O
re-executed	O
after	O
return	O
from	O
the	O
interrupt	B-Application
.	O
</s>
<s>
The	O
cycle	O
begins	O
as	O
soon	O
as	O
power	O
is	O
applied	O
to	O
the	O
system	O
,	O
with	O
an	O
initial	O
PC	O
value	O
that	O
is	O
predefined	O
by	O
the	O
system	O
's	O
architecture	O
(	O
for	O
instance	O
,	O
in	O
Intel	B-Device
IA-32	I-Device
CPUs	B-Device
,	O
the	O
predefined	O
PC	O
value	O
is	O
0xfffffff0	O
)	O
.	O
</s>
<s>
Typically	O
,	O
this	O
address	O
points	O
to	O
a	O
set	O
of	O
instructions	O
in	O
read-only	B-Device
memory	I-Device
(	O
ROM	B-Device
)	O
,	O
which	O
begins	O
the	O
process	O
of	O
loading	O
(	O
or	O
booting	B-Operating_System
)	O
the	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
The	O
PC	O
is	O
incremented	O
so	O
that	O
it	O
points	O
to	O
the	O
next	B-General_Concept
instruction	I-General_Concept
.	O
</s>
<s>
This	O
step	O
prepares	O
the	O
CPU	B-Device
for	O
the	O
next	O
cycle	O
.	O
</s>
<s>
The	O
control	B-General_Concept
unit	I-General_Concept
fetches	O
the	O
instruction	O
's	O
address	O
from	O
the	O
memory	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
The	O
decoding	O
process	O
allows	O
the	O
CPU	B-Device
to	O
determine	O
what	O
instruction	O
is	O
to	O
be	O
performed	O
so	O
that	O
the	O
CPU	B-Device
can	O
tell	O
how	O
many	O
operands	O
it	O
needs	O
to	O
fetch	O
in	O
order	O
to	O
perform	O
the	O
instruction	O
.	O
</s>
<s>
The	O
decoding	O
is	O
typically	O
performed	O
by	O
binary	O
decoders	O
in	O
the	O
CPU	B-Device
's	O
control	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
Indirect	O
memory	O
operation	O
-	O
The	O
effective	B-Language
address	I-Language
is	O
read	O
from	O
memory	O
.	O
</s>
<s>
If	O
it	O
is	O
an	O
I/O	O
or	O
register	B-General_Concept
instruction	O
,	O
the	O
computer	O
checks	O
its	O
type	O
and	O
executes	O
the	O
instruction	O
.	O
</s>
<s>
The	O
CPU	B-Device
sends	O
the	O
decoded	O
instruction	O
as	O
a	O
set	O
of	O
control	O
signals	O
to	O
the	O
corresponding	O
computer	O
components	O
.	O
</s>
<s>
This	O
is	O
the	O
only	O
stage	O
of	O
the	O
instruction	B-General_Concept
cycle	I-General_Concept
that	O
is	O
useful	O
from	O
the	O
perspective	O
of	O
the	O
end-user	O
.	O
</s>
