<s>
Instruction-level	B-Operating_System
parallelism	I-Operating_System
(	O
ILP	O
)	O
is	O
the	O
parallel	B-Operating_System
or	O
simultaneous	O
execution	O
of	O
a	O
sequence	O
of	O
instructions	B-General_Concept
in	O
a	O
computer	B-Application
program	I-Application
.	O
</s>
<s>
More	O
specifically	O
ILP	O
refers	O
to	O
the	O
average	O
number	O
of	O
instructions	B-General_Concept
run	O
per	O
step	O
of	O
this	O
parallel	B-Operating_System
execution	O
.	O
</s>
<s>
ILP	O
must	O
not	O
be	O
confused	O
with	O
concurrency	B-Operating_System
.	O
</s>
<s>
In	O
ILP	O
there	O
is	O
a	O
single	O
specific	O
thread	B-Operating_System
of	I-Operating_System
execution	I-Operating_System
of	O
a	O
process	B-Operating_System
.	O
</s>
<s>
On	O
the	O
other	O
hand	O
,	O
concurrency	B-Operating_System
involves	O
the	O
assignment	O
of	O
multiple	O
threads	B-Operating_System
to	O
a	O
CPU	B-General_Concept
's	O
core	O
in	O
a	O
strict	O
alternation	O
,	O
or	O
in	O
true	O
parallelism	B-Operating_System
if	O
there	O
are	O
enough	O
CPU	B-General_Concept
cores	O
,	O
ideally	O
one	O
core	O
for	O
each	O
runnable	O
thread	B-Operating_System
.	O
</s>
<s>
There	O
are	O
two	O
approaches	O
to	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
:	O
hardware	B-Architecture
and	O
software	O
.	O
</s>
<s>
Hardware	B-Architecture
level	O
works	O
upon	O
dynamic	O
parallelism	B-Operating_System
,	O
whereas	O
the	O
software	O
level	O
works	O
on	O
static	O
parallelism	B-Operating_System
.	O
</s>
<s>
Dynamic	O
parallelism	B-Operating_System
means	O
the	O
processor	B-General_Concept
decides	O
at	O
run	B-Library
time	I-Library
which	O
instructions	B-General_Concept
to	O
execute	O
in	O
parallel	B-Operating_System
,	O
whereas	O
static	O
parallelism	B-Operating_System
means	O
the	O
compiler	B-Language
decides	O
which	O
instructions	B-General_Concept
to	O
execute	O
in	O
parallel	B-Operating_System
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
processor	B-General_Concept
works	O
on	O
the	O
dynamic	O
sequence	O
of	O
parallel	B-Operating_System
execution	O
,	O
but	O
the	O
Itanium	B-General_Concept
processor	B-General_Concept
works	O
on	O
the	O
static	O
level	O
parallelism	B-Operating_System
.	O
</s>
<s>
If	O
we	O
assume	O
that	O
each	O
operation	O
can	O
be	O
completed	O
in	O
one	O
unit	O
of	O
time	O
then	O
these	O
three	O
instructions	B-General_Concept
can	O
be	O
completed	O
in	O
a	O
total	O
of	O
two	O
units	O
of	O
time	O
,	O
giving	O
an	O
ILP	O
of	O
3/2	O
.	O
</s>
<s>
A	O
goal	O
of	O
compiler	B-Language
and	O
processor	B-General_Concept
designers	O
is	O
to	O
identify	O
and	O
take	O
advantage	O
of	O
as	O
much	O
ILP	O
as	O
possible	O
.	O
</s>
<s>
Ordinary	O
programs	O
are	O
typically	O
written	O
under	O
a	O
sequential	O
execution	O
model	O
where	O
instructions	B-General_Concept
execute	O
one	O
after	O
the	O
other	O
and	O
in	O
the	O
order	O
specified	O
by	O
the	O
programmer	O
.	O
</s>
<s>
ILP	O
allows	O
the	O
compiler	B-Language
and	O
the	O
processor	B-General_Concept
to	O
overlap	O
the	O
execution	O
of	O
multiple	O
instructions	B-General_Concept
or	O
even	O
to	O
change	O
the	O
order	O
in	O
which	O
instructions	B-General_Concept
are	O
executed	O
.	O
</s>
<s>
However	O
,	O
workloads	O
such	O
as	O
cryptography	O
may	O
exhibit	O
much	O
less	O
parallelism	B-Operating_System
.	O
</s>
<s>
Instruction	B-General_Concept
pipelining	I-General_Concept
where	O
the	O
execution	O
of	O
multiple	O
instructions	B-General_Concept
can	O
be	O
partially	O
overlapped	O
.	O
</s>
<s>
Superscalar	B-General_Concept
execution	I-General_Concept
,	O
VLIW	B-General_Concept
,	O
and	O
the	O
closely	O
related	O
explicitly	B-General_Concept
parallel	I-General_Concept
instruction	I-General_Concept
computing	I-General_Concept
concepts	O
,	O
in	O
which	O
multiple	O
execution	B-General_Concept
units	I-General_Concept
are	O
used	O
to	O
execute	O
multiple	O
instructions	B-General_Concept
in	O
parallel	B-Operating_System
.	O
</s>
<s>
Out-of-order	B-General_Concept
execution	I-General_Concept
where	O
instructions	B-General_Concept
execute	O
in	O
any	O
order	O
that	O
does	O
not	O
violate	O
data	B-Operating_System
dependencies	I-Operating_System
.	O
</s>
<s>
Note	O
that	O
this	O
technique	O
is	O
independent	O
of	O
both	O
pipelining	O
and	O
superscalar	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
Current	O
implementations	O
of	O
out-of-order	B-General_Concept
execution	I-General_Concept
dynamically	B-Library
(	O
i.e.	O
,	O
while	O
the	O
program	O
is	O
executing	O
and	O
without	O
any	O
help	O
from	O
the	O
compiler	B-Language
)	O
extract	O
ILP	O
from	O
ordinary	O
programs	O
.	O
</s>
<s>
An	O
alternative	O
is	O
to	O
extract	O
this	O
parallelism	B-Operating_System
at	O
compile	B-Application
time	I-Application
and	O
somehow	O
convey	O
this	O
information	O
to	O
the	O
hardware	B-Architecture
.	O
</s>
<s>
Due	O
to	O
the	O
complexity	O
of	O
scaling	O
the	O
out-of-order	B-General_Concept
execution	I-General_Concept
technique	O
,	O
the	O
industry	O
has	O
re-examined	O
instruction	B-General_Concept
sets	I-General_Concept
which	O
explicitly	O
encode	O
multiple	O
independent	O
operations	O
per	O
instruction	O
.	O
</s>
<s>
Register	B-Architecture
renaming	I-Architecture
which	O
refers	O
to	O
a	O
technique	O
used	O
to	O
avoid	O
unnecessary	O
serialization	O
of	O
program	O
operations	O
imposed	O
by	O
the	O
reuse	O
of	O
registers	O
by	O
those	O
operations	O
,	O
used	O
to	O
enable	O
out-of-order	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
Speculative	B-General_Concept
execution	I-General_Concept
which	O
allows	O
the	O
execution	O
of	O
complete	O
instructions	B-General_Concept
or	O
parts	O
of	O
instructions	B-General_Concept
before	O
being	O
certain	O
whether	O
this	O
execution	O
should	O
take	O
place	O
.	O
</s>
<s>
A	O
commonly	O
used	O
form	O
of	O
speculative	B-General_Concept
execution	I-General_Concept
is	O
control	O
flow	O
speculation	O
where	O
instructions	B-General_Concept
past	O
a	O
control	O
flow	O
instruction	O
(	O
e.g.	O
,	O
a	O
branch	O
)	O
are	O
executed	O
before	O
the	O
target	O
of	O
the	O
control	O
flow	O
instruction	O
is	O
determined	O
.	O
</s>
<s>
Several	O
other	O
forms	O
of	O
speculative	B-General_Concept
execution	I-General_Concept
have	O
been	O
proposed	O
and	O
are	O
in	O
use	O
including	O
speculative	B-General_Concept
execution	I-General_Concept
driven	O
by	O
value	O
prediction	O
,	O
memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
and	O
cache	O
latency	O
prediction	O
.	O
</s>
<s>
Branch	B-General_Concept
prediction	I-General_Concept
which	O
is	O
used	O
to	O
avoid	O
stalling	O
for	O
control	O
dependencies	O
to	O
be	O
resolved	O
.	O
</s>
<s>
Branch	B-General_Concept
prediction	I-General_Concept
is	O
used	O
with	O
speculative	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
It	O
is	O
known	O
that	O
the	O
ILP	O
is	O
exploited	O
by	O
both	O
the	O
compiler	B-Language
and	O
hardware	B-Architecture
support	O
but	O
the	O
compiler	B-Language
also	O
provides	O
inherent	O
and	O
implicit	O
ILP	O
in	O
programs	O
to	O
hardware	B-Architecture
by	O
compile-time	B-Application
optimizations	O
.	O
</s>
<s>
Dataflow	B-General_Concept
architectures	I-General_Concept
are	O
another	O
class	O
of	O
architectures	O
where	O
ILP	O
is	O
explicitly	O
specified	O
,	O
for	O
a	O
recent	O
example	O
see	O
the	O
TRIPS	B-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
In	O
recent	O
years	O
,	O
ILP	O
techniques	O
have	O
been	O
used	O
to	O
provide	O
performance	O
improvements	O
in	O
spite	O
of	O
the	O
growing	O
disparity	O
between	O
processor	B-General_Concept
operating	O
frequencies	O
and	O
memory	O
access	O
times	O
(	O
early	O
ILP	O
designs	O
such	O
as	O
the	O
IBM	B-Device
System/360	I-Device
Model	I-Device
91	I-Device
used	O
ILP	O
techniques	O
to	O
overcome	O
the	O
limitations	O
imposed	O
by	O
a	O
relatively	O
small	O
register	O
file	O
)	O
.	O
</s>
<s>
Presently	O
,	O
a	O
cache	O
miss	O
penalty	O
to	O
main	O
memory	O
costs	O
several	O
hundreds	O
of	O
CPU	B-General_Concept
cycles	O
.	O
</s>
<s>
Moreover	O
,	O
the	O
complexity	O
and	O
often	O
the	O
latency	O
of	O
the	O
underlying	O
hardware	B-Architecture
structures	O
results	O
in	O
reduced	O
operating	O
frequency	O
further	O
reducing	O
any	O
benefits	O
.	O
</s>
<s>
Hence	O
,	O
the	O
aforementioned	O
techniques	O
prove	O
inadequate	O
to	O
keep	O
the	O
CPU	B-General_Concept
from	O
stalling	O
for	O
the	O
off-chip	O
data	O
.	O
</s>
<s>
Instead	O
,	O
the	O
industry	O
is	O
heading	O
towards	O
exploiting	O
higher	O
levels	O
of	O
parallelism	B-Operating_System
that	O
can	O
be	O
exploited	O
through	O
techniques	O
such	O
as	O
multiprocessing	B-Operating_System
and	O
multithreading	B-General_Concept
.	O
</s>
