<s>
I/O	B-Device
Controller	I-Device
Hub	I-Device
(	O
ICH	O
)	O
is	O
a	O
family	O
of	O
Intel	O
southbridge	B-Device
microchips	O
used	O
to	O
manage	O
data	B-General_Concept
communications	I-General_Concept
between	O
a	O
CPU	B-Device
and	O
a	O
motherboard	B-Device
,	O
specifically	O
Intel	B-Device
chipsets	I-Device
based	O
on	O
the	O
Intel	B-Architecture
Hub	I-Architecture
Architecture	I-Architecture
.	O
</s>
<s>
It	O
is	O
designed	O
to	O
be	O
paired	O
with	O
a	O
second	O
support	O
chip	O
known	O
as	O
a	O
northbridge	B-Device
.	O
</s>
<s>
As	O
with	O
any	O
other	O
southbridge	B-Device
,	O
the	O
ICH	O
is	O
used	O
to	O
connect	O
and	O
control	O
peripheral	O
devices	O
.	O
</s>
<s>
As	O
CPU	B-Device
speeds	O
increased	O
data	O
transmission	O
between	O
the	O
CPU	B-Device
and	O
support	O
chipset	B-Device
,	O
the	O
support	O
chipset	B-Device
eventually	O
emerged	O
as	O
a	O
bottleneck	O
between	O
the	O
processor	O
and	O
the	O
motherboard	B-Device
.	O
</s>
<s>
Accordingly	O
,	O
starting	O
with	O
the	O
Intel	B-Device
5	I-Device
Series	I-Device
,	O
a	O
new	O
architecture	O
was	O
used	O
that	O
incorporated	O
some	O
functions	O
of	O
the	O
traditional	O
north	O
and	O
south	O
bridge	O
chips	O
onto	O
the	O
CPU	B-Device
itself	O
,	O
with	O
the	O
remaining	O
functions	O
being	O
consolidated	O
into	O
a	O
single	O
Platform	B-Device
Controller	I-Device
Hub	I-Device
(	O
PCH	O
)	O
.	O
</s>
<s>
The	O
first	O
version	O
of	O
the	O
ICH	O
was	O
released	O
in	O
June	O
1999	O
along	O
with	O
the	O
Intel	B-Device
810	I-Device
northbridge	B-Device
.	O
</s>
<s>
While	O
its	O
predecessor	O
,	O
the	O
PIIX	B-Device
,	O
was	O
connected	O
to	O
the	O
northbridge	B-Device
through	O
an	O
internal	O
PCI	B-Protocol
bus	I-Protocol
with	O
a	O
bandwidth	O
of	O
133	O
MB/s	O
,	O
the	O
ICH	O
used	O
a	O
proprietary	O
interface	O
(	O
called	O
by	O
Intel	O
Hub	O
Interface	O
)	O
that	O
linked	O
it	O
to	O
the	O
northbridge	B-Device
through	O
an	O
8-bit	O
wide	O
,	O
266	O
MB/s	O
bus	O
.	O
</s>
<s>
The	O
Hub	O
Interface	O
was	O
a	O
point-to-point	O
connection	O
between	O
different	O
components	O
on	O
the	O
motherboard	B-Device
.	O
</s>
<s>
Another	O
design	O
decision	O
was	O
to	O
substitute	O
the	O
rigid	O
North-South	O
axis	O
on	O
the	O
motherboard	B-Device
with	O
a	O
star	O
structure	O
.	O
</s>
<s>
Thus	O
,	O
the	O
northbridge	B-Device
became	O
the	O
Memory	B-Device
Controller	I-Device
Hub	I-Device
(	O
MCH	O
)	O
or	O
if	O
it	O
had	O
integrated	O
graphics	O
(	O
e.g.	O
,	O
Intel	B-Device
810	I-Device
)	O
,	O
the	O
Graphics	O
and	O
Memory	B-Device
Controller	I-Device
Hub	I-Device
(	O
GMCH	O
)	O
.	O
</s>
<s>
PCI	B-Protocol
Rev	O
2.2	O
compliant	O
with	O
support	O
for	O
33MHz	O
PCI	B-Protocol
operations	O
.	O
</s>
<s>
In	O
early	O
2000	O
Intel	O
had	O
suffered	O
a	O
significant	O
setback	O
with	O
the	O
i820	O
northbridge	B-Device
.	O
</s>
<s>
Customers	O
were	O
not	O
willing	O
to	O
pay	O
the	O
high	O
prices	O
for	O
RDRAM	O
and	O
either	O
bought	O
i810	B-Device
or	O
i440BX	O
motherboards	B-Device
or	O
changed	O
to	O
the	O
competition	O
.	O
</s>
<s>
The	O
hastily	O
developed	O
82815	O
northbridge	B-Device
,	O
which	O
supported	O
PC-133	O
SDRAM	O
,	O
became	O
Intel	O
's	O
method	O
to	O
recover	O
in	O
the	O
middle	O
range	O
segment	O
.	O
</s>
<s>
An	O
ICH2	O
could	O
also	O
be	O
used	O
with	O
Intel	O
's	O
82850	O
chipset	B-Device
,	O
which	O
,	O
like	O
the	O
82820	O
before	O
it	O
,	O
required	O
the	O
use	O
of	O
RDRAM	O
and	O
supported	O
the	O
Pentium	O
4	O
CPU	B-Device
.	O
</s>
<s>
For	O
the	O
first	O
time	O
a	O
Fast	B-Protocol
Ethernet	I-Protocol
chip	O
(	O
82559	O
)	O
was	O
integrated	O
into	O
the	O
southbridge	B-Device
,	O
depending	O
upon	O
an	O
external	O
PHY	O
chip	O
.	O
</s>
<s>
The	O
PATA	B-Protocol
interface	O
was	O
accelerated	O
to	O
ATA/100	O
and	O
the	O
number	O
of	O
USB	B-Protocol
connections	O
was	O
doubled	O
to	O
four	O
.	O
</s>
<s>
In	O
2001	O
,	O
Intel	O
delivered	O
ICH3	O
,	O
which	O
was	O
available	O
in	O
two	O
versions	O
:	O
the	O
server	O
version	O
,	O
ICH3-S	O
,	O
running	O
with	O
the	O
E7501	O
Northbridge	B-Device
,	O
and	O
the	O
mobile	O
version	O
,	O
ICH3-M	O
,	O
which	O
worked	O
with	O
the	O
i830	O
and	O
i845	O
northbridges	B-Device
.	O
</s>
<s>
There	O
is	O
no	O
version	O
for	O
desktop	O
motherboards	B-Device
.	O
</s>
<s>
In	O
comparison	O
with	O
the	O
ICH2	O
,	O
the	O
changes	O
were	O
limited	O
:	O
"	O
Native	O
Mode	O
"	O
support	O
in	O
the	O
PATA	B-Protocol
Controller	O
;	O
up	O
to	O
six	O
USB-1.1	O
devices	O
;	O
SMBus	B-Algorithm
2.0	O
;	O
and	O
the	O
newest	O
SpeedStep	O
version	O
,	O
which	O
allowed	O
power-saving	O
devices	O
to	O
be	O
switched	O
off	O
during	O
operation	O
.	O
</s>
<s>
The	O
ICH4	O
was	O
Intel	O
's	O
southbridge	B-Device
for	O
the	O
year	O
2002	O
.	O
</s>
<s>
The	O
most	O
important	O
innovation	O
was	O
the	O
support	O
of	O
USB	B-Protocol
2.0	O
on	O
all	O
six	O
ports	O
.	O
</s>
<s>
In	O
2003	O
,	O
and	O
in	O
conjunction	O
with	O
the	O
i865	O
and	O
i875	O
northbridges	B-Device
,	O
the	O
ICH5	O
was	O
created	O
.	O
</s>
<s>
The	O
ICH5R	O
variant	O
additionally	O
supported	O
RAID	B-Architecture
0	O
on	O
SATA	O
ports	O
.	O
</s>
<s>
Eight	O
USB-2.0	O
ports	O
were	O
available	O
.	O
</s>
<s>
The	O
chip	O
had	O
full	O
support	O
for	O
ACPI	B-Device
2.0	O
.	O
</s>
<s>
The	O
goal	O
of	O
this	O
CSA	B-Device
technology	O
was	O
to	O
reduce	O
the	O
latencies	O
for	O
Gigabit	O
LAN	O
by	O
direct	O
memory	O
access	O
and	O
to	O
free	O
up	O
bandwidth	O
on	O
the	O
Hub	O
interface	O
between	O
ICH	O
and	O
MCH	O
for	O
non	O
removable	O
disk	O
and	O
PCI	B-Protocol
data	O
traffic	O
.	O
</s>
<s>
Since	O
mid-2004	O
,	O
the	O
large	O
motherboard	B-Device
manufacturers	O
noticed	O
an	O
increased	O
complaint	O
ratio	O
with	O
motherboards	B-Device
equipped	O
with	O
ICH5	O
.	O
</s>
<s>
In	O
particular	O
,	O
when	O
connecting	O
USB	B-Protocol
devices	I-Protocol
via	O
front	O
panels	O
,	O
the	O
chips	O
died	O
by	O
discharges	O
of	O
static	O
electricity	O
.	O
</s>
<s>
Effective	O
ESD	O
preventive	O
measures	O
on	O
USB	B-Protocol
ports	I-Protocol
are	O
difficult	O
and	O
costly	O
,	O
since	O
they	O
can	O
impair	O
the	O
quality	O
of	O
the	O
USB-2.0	O
high-speed	O
signals	O
.	O
</s>
<s>
Many	O
motherboard	B-Device
manufacturers	O
had	O
omitted	O
the	O
necessary	O
high-quality	O
safety	O
devices	O
for	O
front	O
panel	O
connectors	O
for	O
cost	O
reasons	O
.	O
</s>
<s>
ICH6	O
was	O
Intel	O
's	O
first	O
PCI	B-Protocol
Express	O
southbridge	B-Device
.	O
</s>
<s>
It	O
made	O
four	O
PCI	B-Protocol
Express	O
×1	O
ports	O
available	O
.	O
</s>
<s>
The	O
bottleneck	O
Hub	O
interface	O
was	O
replaced	O
by	O
a	O
new	O
Direct	B-Architecture
Media	I-Architecture
Interface	I-Architecture
(	O
in	O
reality	O
a	O
PCI	B-Protocol
Express	O
×4	O
link	O
)	O
with	O
1	O
GB/s	O
of	O
bandwidth	O
per	O
direction	O
.	O
</s>
<s>
In	O
addition	O
,	O
AC'97	O
and	O
the	O
classical	O
PCI	B-Protocol
2.3	I-Protocol
were	O
still	O
supported	O
.	O
</s>
<s>
Two	O
additional	O
SATA	O
ports	O
were	O
added	O
,	O
and	O
one	O
PATA	B-Protocol
channel	O
was	O
removed	O
.	O
</s>
<s>
The	O
ICH6R	O
variant	O
supported	O
RAID	B-Architecture
modes	O
0	O
,	O
1	O
,	O
0+1	O
and	O
the	O
Intel	O
specific	O
"	O
Matrix	O
RAID	B-Architecture
"	O
.	O
</s>
<s>
Originally	O
Intel	O
had	O
planned	O
to	O
bring	O
two	O
further	O
variants	O
under	O
the	O
names	O
ICH6W	O
and	O
ICH6RW	O
to	O
the	O
market	O
,	O
which	O
should	O
contain	O
a	O
software	O
Access	O
Point	O
for	O
a	O
Wireless	B-Architecture
LAN	I-Architecture
.	O
</s>
<s>
Two	O
additional	O
PCI	B-Protocol
express	O
×	O
1-Ports	O
,	O
a	O
SATA	O
2.0	O
Controller	O
for	O
up	O
to	O
300	O
MB/s	O
data	O
transmission	O
rate	O
(	O
the	O
mobile	O
version	O
has	O
this	O
capability	O
disabled	O
)	O
,	O
as	O
well	O
as	O
support	O
for	O
Intel	O
's	O
"	O
Active	O
Management	O
Technology	O
"	O
were	O
added	O
.	O
</s>
<s>
The	O
ICH7R	O
additionally	O
supports	O
RAID	B-Architecture
5	O
.	O
</s>
<s>
The	O
non-mobile	O
ICH8	O
does	O
not	O
have	O
a	O
traditional	O
PATA	B-Protocol
interface	O
,	O
and	O
just	O
one	O
AC'97	O
.	O
</s>
<s>
In	O
practice	O
,	O
most	O
baseboard	O
manufacturers	O
still	O
offered	O
PATA	B-Protocol
appropriate	O
connection	O
types	O
using	O
additional	O
chips	O
from	O
manufacturers	O
such	O
as	O
JMicron	O
or	O
Marvell	O
.	O
</s>
<s>
The	O
ICH8R	O
(	O
RAID	B-Architecture
)	O
and	O
above	O
chips	O
support	O
six	O
SATA	O
devices	O
.	O
</s>
<s>
Additionally	O
the	O
ICH8DH	O
(	O
Digital	O
Home	O
)	O
has	O
Quick	B-Device
Resume	I-Device
and	O
can	O
be	O
used	O
together	O
with	O
the	O
P965	O
and/or	O
G965	O
in	O
Intel	O
Viiv-certified	O
systems	O
.	O
</s>
<s>
The	O
counterpart	O
to	O
the	O
ICH8DO	O
(	O
Digital	O
Office	O
)	O
is	O
the	O
Q965	O
MCH	O
,	O
which	O
together	O
provide	O
Intel	B-Architecture
vPro	I-Architecture
compatibility	O
.	O
</s>
<s>
The	O
ICH9	O
came	O
out	O
in	O
May	O
2007	O
in	O
the	O
P35	B-Device
(	O
Bearlake	O
)	O
chipset	B-Device
.	O
</s>
<s>
It	O
removes	O
all	O
PATA	B-Protocol
support	O
.	O
</s>
<s>
In	O
practice	O
,	O
many	O
motherboard	B-Device
manufacturers	O
continue	O
providing	O
PATA	B-Protocol
support	O
using	O
third-party	O
chips	O
.	O
</s>
<s>
(	O
ICH9	O
)	O
Base	O
officially	O
has	O
neither	O
AHCI	O
or	O
RAID	B-Architecture
support	O
,	O
but	O
with	O
a	O
simple	O
BIOS	O
mod	O
can	O
add	O
support	O
for	O
AHCI	O
.	O
</s>
<s>
Intel	O
launched	O
the	O
ICH10	O
southbridge	B-Device
in	O
June	O
2008	O
with	O
the	O
P45	B-Device
(	O
Eaglelake	O
)	O
chipset	B-Device
.	O
</s>
<s>
ICH10	O
implements	O
the	O
1GB/s	O
bidirectional	O
DMI	B-Architecture
interface	O
to	O
the	O
"	O
northbridge	B-Device
"	O
device	O
.	O
</s>
<s>
ICH10	O
also	O
offers	O
reduced	O
load	O
on	O
CPU	B-Device
and	O
decreased	O
power	O
consumption	O
.	O
</s>
<s>
ICH10	O
does	O
not	O
offer	O
direct	O
PATA	B-Protocol
or	O
LPT	O
support	O
.	O
</s>
<s>
The	O
RAID	B-Architecture
variant	O
also	O
supports	O
a	O
new	O
technology	O
called	O
“	O
Turbo	B-Device
Memory	I-Device
”	O
.	O
</s>
<s>
This	O
allows	O
the	O
use	O
of	O
flash	O
memory	O
on	O
a	O
motherboard	B-Device
for	O
fast	O
caching	O
.	O
</s>
<s>
Six	O
SATA	O
3	O
Gbit/s	O
ports	O
in	O
either	O
legacy	O
IDE	B-Protocol
or	O
AHCI	O
mode	O
.	O
</s>
<s>
As	O
CPU	B-Device
speeds	O
increased	O
,	O
a	O
bottleneck	O
eventually	O
emerged	O
between	O
the	O
processor	O
and	O
the	O
motherboard	B-Device
,	O
due	O
to	O
limitations	O
caused	O
by	O
data	O
transmission	O
between	O
the	O
CPU	B-Device
and	O
southbridge	B-Device
.	O
</s>
<s>
Accordingly	O
,	O
starting	O
with	O
the	O
Intel	B-Device
5	I-Device
Series	I-Device
,	O
a	O
new	O
architecture	O
was	O
used	O
where	O
some	O
functions	O
of	O
the	O
north	O
and	O
south	O
bridge	O
chips	O
were	O
moved	O
to	O
the	O
CPU	B-Device
,	O
and	O
others	O
were	O
consolidated	O
into	O
a	O
Platform	B-Device
Controller	I-Device
Hub	I-Device
(	O
PCH	O
)	O
.	O
</s>
<s>
Some	O
northbridge	B-Device
functions	O
,	O
including	O
the	O
memory	O
controller	O
,	O
the	O
integrated	O
GPU	O
(	O
Intel	B-Application
HD	I-Application
Graphics	I-Application
)	O
,	O
the	O
graphics	O
card	O
interface	O
(	O
PCIe	O
x16	O
)	O
,	O
were	O
integrated	O
into	O
the	O
CPU	B-Device
,	O
while	O
the	O
PCH	O
took	O
over	O
the	O
remaining	O
functions	O
in	O
addition	O
to	O
the	O
traditional	O
roles	O
of	O
the	O
southbridge	B-Device
.	O
</s>
<s>
The	O
northbridge	B-Device
was	O
therefore	O
eliminated	O
.	O
</s>
<s>
Other	O
northbridge	B-Device
functions	O
and	O
all	O
southbridge	B-Device
functions	O
were	O
migrated	O
to	O
a	O
new	O
Platform	B-Device
Controller	I-Device
Hub	I-Device
.	O
</s>
<s>
These	O
included	O
clocking	O
(	O
the	O
system	B-Operating_System
clock	I-Operating_System
)	O
,	O
Flexible	B-Device
Display	I-Device
Interface	I-Device
(	O
FDI	O
)	O
and	O
Direct	B-Architecture
Media	I-Architecture
Interface	I-Architecture
(	O
DMI	B-Architecture
)	O
.	O
</s>
<s>
The	O
FDI	O
is	O
only	O
used	O
when	O
the	O
chipset	B-Device
requires	O
supporting	O
a	O
CPU	B-Device
with	O
integrated	O
graphics	O
.	O
</s>
