<s>
The	O
zEC12	O
microprocessor	B-Architecture
(	O
zEnterprise	O
EC12	O
or	O
just	O
z12	O
)	O
is	O
a	O
chip	O
made	O
by	O
IBM	O
for	O
their	O
zEnterprise	O
EC12	O
and	O
zEnterprise	O
BC12	O
mainframe	B-Architecture
computers	I-Architecture
,	O
announced	O
on	O
August	O
28	O
,	O
2012	O
.	O
</s>
<s>
It	O
is	O
manufactured	O
at	O
the	O
East	O
Fishkill	O
,	O
New	O
York	O
fabrication	B-Architecture
plant	O
(	O
previously	O
owned	O
by	O
IBM	O
but	O
production	O
will	O
continue	O
for	O
ten	O
years	O
by	O
new	O
owner	O
GlobalFoundries	O
)	O
.	O
</s>
<s>
IBM	O
stated	O
that	O
it	O
was	O
the	O
world	O
's	O
fastest	O
microprocessor	B-Architecture
and	O
is	O
about	O
25%	O
faster	O
than	O
its	O
predecessor	O
the	O
z196	B-Device
.	O
</s>
<s>
The	O
chip	O
measures	O
597.24mm2	O
and	O
consists	O
of	O
2.75	O
billion	O
transistors	B-Application
fabricated	O
in	O
IBM	O
's	O
32	B-Algorithm
nm	I-Algorithm
CMOS	B-Device
silicon	B-Algorithm
on	I-Algorithm
insulator	I-Algorithm
fabrication	B-Architecture
process	I-Architecture
,	O
supporting	O
speeds	O
of	O
5.5GHz	O
,	O
the	O
highest	O
clock	O
speed	O
CPU	O
ever	O
produced	O
for	O
commercial	O
sale	O
.	O
</s>
<s>
The	O
processor	O
implements	O
the	O
CISC	B-Architecture
z/Architecture	B-Device
with	O
a	O
superscalar	B-General_Concept
,	O
out-of-order	B-General_Concept
pipeline	B-General_Concept
and	O
some	O
new	O
instructions	O
mainly	O
related	O
to	O
transactional	B-Operating_System
execution	I-Operating_System
.	O
</s>
<s>
The	O
cores	B-Architecture
have	O
numerous	O
other	O
enhancements	O
such	O
as	O
better	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
out	B-General_Concept
of	I-General_Concept
order	I-General_Concept
execution	I-General_Concept
and	O
one	O
dedicated	O
co-processor	O
for	O
compression	O
and	O
cryptography	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
pipeline	I-General_Concept
has	O
15	O
to	O
17	O
stages	O
;	O
the	O
instruction	O
queue	O
can	O
hold	O
40	O
instructions	O
;	O
and	O
up	O
to	O
90	O
instructions	O
can	O
be	O
"	O
in	O
flight	O
"	O
.	O
</s>
<s>
It	O
has	O
six	O
cores	B-Architecture
,	O
each	O
with	O
a	O
private	O
64	O
KB	O
L1	B-General_Concept
instruction	I-General_Concept
cache	I-General_Concept
,	O
a	O
private	O
96	O
KB	O
L1	O
data	B-General_Concept
cache	I-General_Concept
,	O
a	O
private	O
1	O
MB	O
L2	B-General_Concept
cache	I-General_Concept
instruction	O
cache	O
,	O
and	O
a	O
private	O
1	O
MB	O
L2	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Each	O
core	O
has	O
six	O
RISC-like	O
execution	O
units	O
,	O
including	O
two	O
integer	B-General_Concept
units	I-General_Concept
,	O
two	O
load-store	B-Architecture
units	I-Architecture
,	O
one	O
binary	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
and	O
one	O
decimal	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
Attached	O
to	O
each	O
core	O
is	O
a	O
special	O
co-processor	O
accelerator	O
unit	O
;	O
in	O
the	O
previous	O
z	O
CPU	O
there	O
were	O
two	O
shared	O
by	O
all	O
four	O
cores	B-Architecture
.	O
</s>
<s>
The	O
zEC12	O
chip	O
has	O
on	O
board	O
multi-channel	O
DDR3	O
RAM	O
memory	B-General_Concept
controller	I-General_Concept
supporting	O
a	O
RAID	B-Architecture
like	O
configuration	O
to	O
recover	O
from	O
memory	O
faults	O
.	O
</s>
<s>
Even	O
though	O
each	O
chip	O
has	O
48	O
MB	O
L3	O
cache	O
shared	O
by	O
the	O
6	O
cores	B-Architecture
and	O
other	O
on-die	O
facilities	O
for	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
(	O
SMP	O
)	O
,	O
there	O
are	O
2	O
dedicated	O
companion	O
chips	O
called	O
the	O
Shared	B-General_Concept
Cache	I-General_Concept
(	O
SC	O
)	O
that	O
each	O
adds	O
192	O
MB	O
off-die	O
L4	B-General_Concept
cache	I-General_Concept
for	O
a	O
total	O
of	O
384	O
MB	O
L4	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
L4	B-General_Concept
cache	I-General_Concept
is	O
shared	O
by	O
all	O
processors	O
in	O
the	O
book	O
.	O
</s>
<s>
The	O
SC	O
chips	O
are	O
manufactured	O
on	O
the	O
same	O
process	O
as	O
the	O
zEC12	O
processor	O
chips	O
,	O
measures	O
28.4	O
x	O
23.9	O
mm	O
and	O
have	O
3.3	O
billion	O
transistors	B-Application
each	O
.	O
</s>
<s>
The	O
zEnterprise	O
System	O
EC12	O
uses	O
multi-chip	B-Algorithm
modules	I-Algorithm
(	O
MCMs	O
)	O
which	O
allows	O
for	O
six	O
zEC12	O
chips	O
to	O
be	O
on	O
a	O
single	O
module	O
.	O
</s>
<s>
Each	O
MCM	O
has	O
two	O
shared	B-General_Concept
cache	I-General_Concept
chips	O
allowing	O
processors	O
on	O
the	O
MCM	O
to	O
be	O
connected	O
with	O
40	O
GB/s	O
links	O
.	O
</s>
<s>
The	O
different	O
models	O
of	O
the	O
zEnterprise	O
System	O
have	O
a	O
different	O
number	O
of	O
active	O
cores	B-Architecture
.	O
</s>
