<s>
The	O
z196	O
microprocessor	B-Architecture
is	O
a	O
chip	O
made	O
by	O
IBM	O
for	O
their	O
zEnterprise	O
196	O
and	O
zEnterprise	O
114	O
mainframe	B-Architecture
computers	I-Architecture
,	O
announced	O
on	O
July	O
22	O
,	O
2010	O
.	O
</s>
<s>
Manufactured	O
at	O
IBM	O
's	O
Fishkill	O
,	O
New	O
York	O
fabrication	B-Architecture
plant	O
,	O
the	O
processor	O
began	O
shipping	O
on	O
September	O
10	O
,	O
2010	O
.	O
</s>
<s>
IBM	O
stated	O
that	O
it	O
was	O
the	O
world	O
's	O
fastest	O
microprocessor	B-Architecture
at	O
the	O
time	O
.	O
</s>
<s>
The	O
chip	O
measures	O
512.3mm2	O
and	O
consists	O
of	O
1.4	O
billion	O
transistors	B-Application
fabricated	O
in	O
IBM	O
's	O
45	B-Algorithm
nm	I-Algorithm
CMOS	B-Device
silicon	B-Algorithm
on	I-Algorithm
insulator	I-Algorithm
fabrication	B-Architecture
process	I-Architecture
,	O
supporting	O
speeds	O
of	O
5.2GHz	O
:	O
at	O
the	O
time	O
,	O
the	O
highest	O
clock	O
speed	O
CPU	O
ever	O
produced	O
for	O
commercial	O
sale	O
.	O
</s>
<s>
The	O
processor	O
implements	O
the	O
CISC	B-Architecture
z/Architecture	B-Device
with	O
a	O
new	O
superscalar	B-General_Concept
,	O
out-of-order	B-General_Concept
pipeline	B-General_Concept
and	O
100	O
new	O
instructions	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
pipeline	I-General_Concept
has	O
15	O
to	O
17	O
stages	O
;	O
the	O
instruction	O
queue	O
can	O
hold	O
40	O
instructions	O
;	O
and	O
up	O
to	O
72	O
instructions	O
can	O
be	O
"	O
in	O
flight	O
"	O
.	O
</s>
<s>
It	O
has	O
four	O
cores	B-Architecture
,	O
each	O
with	O
a	O
private	O
64	O
KB	O
L1	B-General_Concept
instruction	I-General_Concept
cache	I-General_Concept
,	O
a	O
private	O
128	O
KB	O
L1	O
data	B-General_Concept
cache	I-General_Concept
and	O
a	O
private	O
1.5	O
MB	O
L2	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Each	O
core	O
has	O
six	O
RISC-like	O
execution	O
units	O
,	O
including	O
two	O
integer	B-General_Concept
units	I-General_Concept
,	O
two	O
load-store	B-Architecture
units	I-Architecture
,	O
one	O
binary	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
and	O
one	O
decimal	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
The	O
z196	O
chip	O
has	O
on	O
board	O
DDR3	O
RAM	O
memory	B-General_Concept
controller	I-General_Concept
supporting	O
a	O
RAID	B-Architecture
like	O
configuration	O
to	O
recover	O
from	O
memory	O
faults	O
.	O
</s>
<s>
Even	O
though	O
the	O
z196	O
processor	O
has	O
on-die	O
facilities	O
for	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
(	O
SMP	O
)	O
,	O
there	O
are	O
2	O
dedicated	O
companion	O
chips	O
called	O
the	O
Shared	B-General_Concept
Cache	I-General_Concept
(	O
SC	O
)	O
that	O
each	O
adds	O
96	O
MB	O
off-die	O
L4	B-General_Concept
cache	I-General_Concept
for	O
a	O
total	O
of	O
192	O
MB	O
L4	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
L4	B-General_Concept
cache	I-General_Concept
is	O
shared	O
by	O
all	O
processors	O
in	O
the	O
book	O
.	O
</s>
<s>
The	O
SC	O
chip	O
consists	O
of	O
1.5	O
billion	O
transistors	B-Application
and	O
measures	O
478.8mm2	O
,	O
manufactured	O
with	O
the	O
same	O
45nm	B-Algorithm
process	O
as	O
the	O
z196	O
chip	O
.	O
</s>
<s>
Each	O
chip	O
also	O
has	O
24	O
MB	O
L3	O
cache	O
shared	O
by	O
the	O
4	O
cores	B-Architecture
on	O
the	O
chip	O
.	O
</s>
<s>
The	O
zEnterprise	O
System	O
z196	O
uses	O
multi-chip	B-Algorithm
modules	I-Algorithm
(	O
MCMs	O
)	O
which	O
allows	O
for	O
six	O
z196	O
chips	O
to	O
be	O
on	O
a	O
single	O
module	O
.	O
</s>
<s>
Each	O
MCM	O
has	O
two	O
shared	B-General_Concept
cache	I-General_Concept
chips	O
allowing	O
processors	O
on	O
the	O
MCM	O
to	O
be	O
connected	O
with	O
40	O
GB/s	O
links	O
.	O
</s>
<s>
The	O
different	O
models	O
of	O
the	O
zEnterprise	O
System	O
have	O
a	O
different	O
number	O
of	O
active	O
cores	B-Architecture
.	O
</s>
<s>
Two	O
SCMs	O
and	O
one	O
Shared	B-General_Concept
Cache	I-General_Concept
chip	O
is	O
mounted	O
together	O
in	O
a	O
processor	O
drawer	O
.	O
</s>
