<s>
The	O
z15	O
is	O
a	O
microprocessor	B-Architecture
made	O
by	O
IBM	O
for	O
their	O
z15	O
mainframe	B-Architecture
computers	I-Architecture
,	O
announced	O
on	O
September	O
12	O
,	O
2019	O
.	O
</s>
<s>
The	O
z15	O
cores	O
support	O
two-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
.	O
</s>
<s>
The	O
cores	O
implement	O
the	O
CISC	B-Architecture
z/Architecture	B-Device
with	O
a	O
superscalar	B-General_Concept
,	O
out-of-order	B-General_Concept
pipeline	B-General_Concept
.	O
</s>
<s>
New	O
in	O
z15	O
is	O
an	O
on-chip	O
Nest	O
Accelerator	O
Unit	O
,	O
shared	O
by	O
all	O
cores	O
,	O
to	O
accelerate	O
compression	B-General_Concept
.	O
</s>
<s>
level	O
3	O
)	O
is	O
doubled	O
from	O
the	O
previous	O
generation	O
z14	B-Device
,	O
while	O
the	O
"	O
L4	O
Cache	O
increased	O
from	O
672MB	O
to	O
960MB	O
,	O
or	O
+43%	O
"	O
with	O
the	O
new	O
add-on	O
chip	O
System	O
Controller	O
(	O
SC	O
)	O
SCM	O
.	O
</s>
<s>
Both	O
it	O
and	O
all	O
levels	O
of	O
cache	O
in	O
the	O
main	O
processor	O
from	O
level	O
1	O
use	O
eDRAM	O
,	O
instead	O
of	O
the	O
traditionally	O
used	O
SRAM	B-Architecture
.	O
</s>
