<s>
The	O
z14	O
is	O
a	O
microprocessor	B-Architecture
made	O
by	O
IBM	O
for	O
their	O
z14	O
mainframe	B-Architecture
computers	I-Architecture
,	O
announced	O
on	O
July	O
17	O
,	O
2017	O
.	O
</s>
<s>
Manufactured	O
at	O
GlobalFoundries	O
 '	O
East	O
Fishkill	O
,	O
New	O
York	O
fabrication	B-Architecture
plant	O
.	O
</s>
<s>
IBM	O
stated	O
that	O
it	O
is	O
the	O
world	O
's	O
fastest	O
microprocessor	B-Architecture
by	O
clock	O
rate	O
at	O
5.2GHz	O
,	O
with	O
a	O
10%	O
increased	O
performance	O
per	O
core	O
and	O
30%	O
for	O
the	O
whole	O
chip	O
compared	O
to	O
its	O
predecessor	O
the	O
z13	B-Device
.	O
</s>
<s>
The	O
Processor	O
Unit	O
chip	O
(	O
PU	O
chip	O
)	O
has	O
an	O
area	O
of	O
696mm2	O
(	O
25.3	O
×	O
27.5mm	O
)	O
and	O
consists	O
of	O
6.1	O
billion	O
transistors	B-Application
.	O
</s>
<s>
It	O
is	O
fabricated	O
using	O
GlobalFoundries	O
 '	O
14	O
nm	O
FinFET	O
silicon	B-Algorithm
on	I-Algorithm
insulator	I-Algorithm
fabrication	B-Architecture
process	I-Architecture
,	O
using	O
17	O
layers	O
of	O
metal	O
and	O
supporting	O
speeds	O
of	O
5.2GHz	O
,	O
which	O
is	O
higher	O
than	O
its	O
predecessor	O
,	O
the	O
z13	B-Device
.	O
</s>
<s>
The	O
z14	O
cores	O
support	O
two-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
for	O
more	O
applications	O
than	O
previously	O
available	O
.	O
</s>
<s>
The	O
PU	O
chip	O
is	O
packaged	O
in	O
a	O
single-chip	O
module	O
,	O
which	O
is	O
the	O
same	O
as	O
its	O
predecessor	O
,	O
but	O
a	O
departure	O
from	O
previous	O
designs	O
which	O
were	O
mounted	O
on	O
large	O
multi-chip	B-Algorithm
modules	I-Algorithm
.	O
</s>
<s>
A	O
computer	O
drawer	O
consists	O
of	O
six	O
PU	O
chips	O
and	O
one	O
Storage	O
Controller	O
(	O
SC	O
)	O
chip	O
containing	O
the	O
L4	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
cores	O
implement	O
the	O
CISC	B-Architecture
z/Architecture	B-Device
with	O
a	O
superscalar	B-General_Concept
,	O
out-of-order	B-General_Concept
pipeline	B-General_Concept
.	O
</s>
<s>
New	O
in	O
z14	O
is	O
a	O
cryptographic	O
coprocessor	B-General_Concept
,	O
called	O
CPACF	O
,	O
attached	O
to	O
each	O
core	O
,	O
used	O
for	O
random	O
number	O
generation	O
,	O
hashing	B-Error_Name
,	O
encryption	O
and	O
decrypting	O
and	O
compression	O
.	O
</s>
<s>
Further	O
enhancements	O
include	O
an	O
optimization	O
of	O
the	O
core	O
's	O
pipeline	B-General_Concept
,	O
doubling	O
the	O
on-chip	B-General_Concept
caches	I-General_Concept
,	O
better	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
a	O
new	O
decimal	O
arithmetic	O
SIMD	B-Device
engine	O
designed	O
to	O
boost	O
COBOL	B-Application
and	O
PL/I	B-Language
code	O
,	O
a	O
"	O
guarded	O
storage	O
facility	O
"	O
that	O
helps	O
Java	B-Language
applications	O
during	O
garbage	B-General_Concept
collection	I-General_Concept
,	O
and	O
other	O
enhancements	O
that	O
increase	O
the	O
cores	O
 '	O
performance	O
compared	O
to	O
the	O
predecessors	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
pipeline	I-General_Concept
has	O
an	O
instruction	O
queue	O
that	O
can	O
fetch	O
6	O
instructions	O
per	O
cycle	O
;	O
and	O
issue	O
up	O
to	O
10	O
instructions	O
per	O
cycle	O
.	O
</s>
<s>
Each	O
core	O
has	O
a	O
private	O
128	O
KB	O
L1	O
instruction	O
cache	B-General_Concept
,	O
a	O
private	O
128KB	O
L1	O
data	B-General_Concept
cache	I-General_Concept
,	O
a	O
private	O
2	O
MB	O
L2	O
instruction	O
cache	B-General_Concept
,	O
and	O
a	O
private	O
4MB	O
L2	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
In	O
addition	O
,	O
there	O
is	O
a	O
128MB	O
shared	O
L3	O
cache	B-General_Concept
implemented	O
in	O
eDRAM	O
.	O
</s>
<s>
The	O
z14	O
chip	O
has	O
on	O
board	O
multi-channel	O
DDR4	O
RAM	O
memory	B-General_Concept
controller	I-General_Concept
supporting	O
a	O
RAID-like	O
configuration	O
to	O
recover	O
from	O
memory	O
faults	O
.	O
</s>
<s>
Even	O
though	O
each	O
PU	O
chip	O
has	O
128MB	O
L3	O
cache	B-General_Concept
shared	O
by	O
the	O
10	O
cores	O
and	O
other	O
on-die	O
facilities	O
,	O
the	O
SC	O
chip	O
adds	O
672MB	O
off-die	O
eDRAM	O
L4	B-General_Concept
cache	I-General_Concept
shared	O
by	O
the	O
six	O
PU	O
chips	O
in	O
the	O
drawer	O
.	O
</s>
<s>
The	O
SC	O
chip	O
is	O
manufactured	O
on	O
the	O
same	O
14nm	O
process	O
as	O
the	O
z14	O
PU	O
chips	O
,	O
has	O
17	O
metal	O
layers	O
,	O
similarly	O
measures	O
25.3	O
×	O
27.5mm	O
(	O
696mm2	O
)	O
,	O
but	O
consists	O
of	O
9.7	O
billion	O
transistors	B-Application
due	O
to	O
amount	O
of	O
L4	O
memory	O
and	O
runs	O
at	O
half	O
the	O
clock	O
frequency	O
of	O
the	O
PU	O
chip	O
.	O
</s>
