<s>
The	O
z13	O
is	O
a	O
microprocessor	B-Architecture
made	O
by	O
IBM	O
for	O
their	O
z13	O
mainframe	B-Architecture
computers	I-Architecture
,	O
announced	O
on	O
January	O
14	O
,	O
2015	O
.	O
</s>
<s>
Manufactured	O
at	O
GlobalFoundries	O
 '	O
East	O
Fishkill	O
,	O
New	O
York	O
fabrication	B-Architecture
plant	O
(	O
formerly	O
IBM	O
's	O
own	O
plant	O
)	O
.	O
</s>
<s>
IBM	O
stated	O
that	O
it	O
is	O
the	O
world	O
's	O
fastest	O
microprocessor	B-Architecture
and	O
is	O
about	O
10%	O
faster	O
than	O
its	O
predecessor	O
the	O
zEC12	B-Device
in	O
general	O
single-threaded	O
computing	O
,	O
but	O
significantly	O
more	O
when	O
doing	O
specialized	O
tasks	O
.	O
</s>
<s>
The	O
IBM	B-Device
z13	I-Device
is	O
the	O
last	O
z	O
Systems	O
server	O
to	O
support	O
running	O
an	O
operating	O
system	O
in	O
ESA/390	O
architecture	O
mode	O
.	O
</s>
<s>
The	O
Processor	O
Unit	O
chip	O
(	O
PU	O
chip	O
)	O
has	O
an	O
area	O
of	O
678mm2	O
and	O
contains	O
3.99	O
billion	O
transistors	B-Application
.	O
</s>
<s>
It	O
is	O
fabricated	O
using	O
IBM	O
's	O
22	O
nm	O
CMOS	B-Device
silicon	B-Algorithm
on	I-Algorithm
insulator	I-Algorithm
fabrication	B-Architecture
process	I-Architecture
,	O
using	O
17	O
metal	O
layers	O
and	O
supporting	O
speeds	O
of	O
5.0GHz	O
,	O
which	O
is	O
less	O
than	O
its	O
predecessor	O
,	O
the	O
zEC12	B-Device
.	O
</s>
<s>
The	O
PU	O
chip	O
is	O
packaged	O
in	O
a	O
single-chip	O
module	O
,	O
a	O
departure	O
from	O
IBM	O
's	O
previous	O
mainframe	B-Architecture
processors	O
,	O
which	O
were	O
mounted	O
on	O
large	O
multi-chip	B-Algorithm
modules	I-Algorithm
.	O
</s>
<s>
The	O
cores	O
implement	O
the	O
CISC	B-Architecture
z/Architecture	B-Device
with	O
a	O
superscalar	B-General_Concept
,	O
out-of-order	B-General_Concept
pipeline	B-General_Concept
.	O
</s>
<s>
It	O
has	O
facilities	O
related	O
to	O
transactional	B-Operating_System
memory	I-Operating_System
,	O
and	O
new	O
features	O
such	O
as	O
two-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
,	O
139	O
new	O
SIMD	B-Device
instructions	O
,	O
data	B-General_Concept
compression	I-General_Concept
,	O
improved	O
cryptography	O
and	O
logical	B-Device
partitioning	I-Device
.	O
</s>
<s>
The	O
cores	O
have	O
numerous	O
other	O
enhancements	O
such	O
as	O
a	O
new	O
superscalar	B-General_Concept
pipeline	B-General_Concept
,	O
on-chip	B-General_Concept
cache	I-General_Concept
design	O
and	O
error	O
correction	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
pipeline	I-General_Concept
has	O
an	O
instruction	O
queue	O
that	O
can	O
fetch	O
6	O
instructions	O
per	O
cycle	O
;	O
and	O
issue	O
up	O
to	O
10	O
instructions	O
per	O
cycle	O
.	O
</s>
<s>
Each	O
core	O
has	O
a	O
private	O
96	O
KB	O
L1	B-General_Concept
instruction	I-General_Concept
cache	I-General_Concept
,	O
a	O
private	O
128KB	O
L1	O
data	B-General_Concept
cache	I-General_Concept
,	O
a	O
private	O
2	O
MB	O
L2	B-General_Concept
cache	I-General_Concept
instruction	O
cache	O
,	O
and	O
a	O
private	O
2MB	O
L2	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
z13	O
chip	O
has	O
on	O
board	O
multi-channel	O
DDR3	O
RAM	O
memory	B-General_Concept
controller	I-General_Concept
supporting	O
a	O
RAID-like	O
configuration	O
to	O
recover	O
from	O
memory	O
faults	O
.	O
</s>
<s>
The	O
z13	O
implementation	O
includes	O
two	O
independent	O
SIMD	B-Device
units	O
to	O
operate	O
on	O
vector	O
data	O
.	O
</s>
<s>
Even	O
though	O
each	O
PU	O
chip	O
has	O
64MB	O
L3	O
cache	O
shared	O
by	O
the	O
8	O
cores	O
and	O
other	O
on-die	O
facilities	O
the	O
SC	O
chip	O
adds	O
480MB	O
off-die	O
L4	B-General_Concept
cache	I-General_Concept
shared	O
by	O
three	O
PU	O
chips	O
.	O
</s>
<s>
The	O
two	O
SC	O
chips	O
add	O
a	O
total	O
of	O
960MB	O
L4	B-General_Concept
cache	I-General_Concept
per	O
drawer	O
.	O
</s>
<s>
The	O
SC	O
chip	O
is	O
manufactured	O
on	O
the	O
same	O
22nm	O
process	O
as	O
the	O
z13	O
PU	O
chips	O
,	O
has	O
15	O
metal	O
layers	O
,	O
measures	O
28.4	O
×	O
23.9mm	O
(	O
678mm2	O
)	O
,	O
consists	O
of	O
7.1	O
billion	O
transistors	B-Application
and	O
runs	O
at	O
half	O
the	O
clock	O
frequency	O
of	O
the	O
CP	O
chip	O
.	O
</s>
