<s>
The	O
z10	O
is	O
a	O
microprocessor	B-Architecture
chip	O
made	O
by	O
IBM	O
for	O
their	O
System	B-Device
z10	I-Device
mainframe	B-Architecture
computers	I-Architecture
,	O
released	O
February	O
26	O
,	O
2008	O
.	O
</s>
<s>
The	O
processor	O
implements	O
the	O
CISC	B-Architecture
z/Architecture	B-Device
and	O
has	O
four	O
cores	B-Architecture
.	O
</s>
<s>
Each	O
core	O
has	O
a	O
64	O
KB	O
L1	B-General_Concept
instruction	I-General_Concept
cache	I-General_Concept
,	O
a	O
128	O
KB	O
L1	O
data	B-General_Concept
cache	I-General_Concept
and	O
a	O
3	O
MB	O
L2	B-General_Concept
cache	I-General_Concept
(	O
called	O
the	O
L1.5	O
cache	O
by	O
IBM	O
)	O
.	O
</s>
<s>
Finally	O
,	O
there	O
is	O
a	O
24	O
MB	O
shared	O
L3	B-General_Concept
cache	I-General_Concept
(	O
referred	O
to	O
as	O
the	O
L2	B-General_Concept
cache	I-General_Concept
by	O
IBM	O
)	O
.	O
</s>
<s>
The	O
chip	O
measures	O
21.7	O
×	O
20.0mm	O
and	O
consists	O
of	O
993	O
million	O
transistors	B-Application
fabricated	O
in	O
IBM	O
's	O
65	B-Algorithm
nm	I-Algorithm
SOI	B-Algorithm
fabrication	B-Architecture
process	I-Architecture
(	O
CMOS	O
11S	O
)	O
,	O
supporting	O
speeds	O
of	O
4.4	O
GHz	O
and	O
above	O
more	O
than	O
twice	O
the	O
clock	O
speed	O
as	O
former	B-Device
mainframes	I-Device
with	O
a	O
15	O
FO4	O
cycle	O
.	O
</s>
<s>
Each	O
z10	O
chip	O
has	O
two	O
48	O
GB/s	O
(	O
48	O
billion	O
bytes	B-Application
per	O
second	O
)	O
SMP	B-Operating_System
hub	O
ports	O
,	O
four	O
13	O
GB/s	O
memory	O
ports	O
,	O
two	O
17	O
GB/s	O
I/O	O
ports	O
,	O
and	O
8765	O
contacts	O
.	O
</s>
<s>
The	O
z10	O
processor	O
was	O
co-developed	O
with	O
and	O
shares	O
many	O
design	O
traits	O
with	O
the	O
POWER6	B-Device
processor	O
,	O
such	O
as	O
fabrication	B-Architecture
technology	O
,	O
logic	O
design	O
,	O
execution	B-General_Concept
unit	I-General_Concept
,	O
floating-point	O
units	O
,	O
bus	O
technology	O
(	O
GX	O
bus	O
)	O
and	O
pipeline	B-General_Concept
design	O
style	O
,	O
i.e.	O
,	O
a	O
high	O
frequency	O
,	O
low	O
latency	O
,	O
deep	O
(	O
14	O
stages	O
in	O
the	O
z10	O
)	O
,	O
in-order	O
pipeline	B-General_Concept
.	O
</s>
<s>
However	O
,	O
the	O
processors	O
are	O
quite	O
dissimilar	O
in	O
other	O
respects	O
,	O
such	O
as	O
cache	O
hierarchy	O
and	O
coherency	B-General_Concept
,	O
SMP	B-Operating_System
topology	O
and	O
protocol	O
,	O
and	O
chip	O
organization	O
.	O
</s>
<s>
The	O
different	O
ISAs	O
result	O
in	O
very	O
different	O
cores	B-Architecture
there	O
are	O
894	O
unique	O
z10	O
instructions	O
,	O
75%	O
of	O
which	O
are	O
implemented	O
entirely	O
in	O
hardware	O
.	O
</s>
<s>
The	O
z/Architecture	B-Device
is	O
a	O
CISC	B-Architecture
architecture	I-Architecture
,	O
backwards	O
compatible	O
to	O
the	O
IBM	B-Application
System/360	I-Application
architecture	O
from	O
the	O
1960s	O
.	O
</s>
<s>
Additions	O
to	O
the	O
z/Architecture	B-Device
from	O
the	O
previous	O
z9	B-Device
EC	I-Device
processor	O
include	O
:	O
</s>
<s>
Even	O
though	O
the	O
z10	O
processor	O
has	O
on-die	O
facilities	O
for	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
(	O
SMP	B-Operating_System
)	O
,	O
there	O
is	O
a	O
dedicated	O
companion	O
chip	O
called	O
the	O
SMP	B-Operating_System
Hub	O
Chip	O
or	O
Storage	O
Control	O
(	O
SC	O
)	O
that	O
adds	O
24	O
MB	O
off-die	O
L3	B-General_Concept
cache	I-General_Concept
and	O
lets	O
it	O
communicate	O
with	O
other	O
z10	O
processors	O
and	O
Hub	O
Chips	O
at	O
48	O
GB/s	O
.	O
</s>
<s>
The	O
Hub	O
Chip	O
consists	O
of	O
1.6	O
billion	O
transistors	B-Application
and	O
measures	O
20.8	O
×	O
21.4mm	O
,	O
with	O
7984	O
interconnects	O
.	O
</s>
<s>
The	O
design	O
allows	O
each	O
processor	O
to	O
share	O
cache	O
across	O
two	O
Hub	O
Chips	O
,	O
for	O
a	O
potential	O
total	O
of	O
48	O
MB	O
of	O
shared	O
L3	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
On	O
the	O
System	B-Device
z10	I-Device
Enterprise	O
Class	O
(	O
EC	O
)	O
the	O
z10	O
processors	O
and	O
the	O
Storage	O
Control	O
(	O
SC	O
)	O
chips	O
are	O
mounted	O
on	O
multi-chip	B-Algorithm
modules	I-Algorithm
(	O
MCMs	O
)	O
.	O
</s>
<s>
Due	O
to	O
redundancy	O
,	O
manufacturing	O
issues	O
,	O
and	O
other	O
operating	O
features	O
,	O
not	O
all	O
cores	B-Architecture
are	O
available	O
to	O
the	O
customer	O
.	O
</s>
<s>
The	O
System	B-Device
z10	I-Device
EC	O
models	O
E12	O
,	O
E26	O
,	O
E40	O
and	O
E56	O
,	O
the	O
MCMs	O
have	O
17	O
available	O
cores	B-Architecture
(	O
one	O
,	O
two	O
,	O
three	O
and	O
four	O
MCMs	O
respectively	O
)	O
,	O
and	O
the	O
model	O
E64	O
have	O
one	O
MCM	O
with	O
17	O
cores	B-Architecture
,	O
and	O
three	O
with	O
20	O
cores	B-Architecture
.	O
</s>
