<s>
Rivina	O
is	O
an	O
experimental	O
64-bit	B-Device
PowerPC	B-Architecture
microprocessor	B-Architecture
built	O
by	O
IBM	O
in	O
2000	O
.	O
</s>
<s>
They	O
were	O
the	O
first	O
microprocessors	B-Architecture
to	O
reach	O
and	O
surpass	O
the	O
1	O
GHz	O
mark	O
.	O
</s>
<s>
The	O
idea	O
was	O
to	O
use	O
aggressive	O
circuit	O
design	O
techniques	O
,	O
a	O
carefully	O
crafted	O
floorplan	O
and	O
microarchitecture	B-General_Concept
while	O
keeping	O
a	O
short	O
six	O
stage	O
pipeline	B-General_Concept
.	O
</s>
<s>
While	O
guTS	O
only	O
supported	O
a	O
subset	O
of	O
about	O
100	O
,	O
mainly	O
integer	O
instructions	O
,	O
of	O
the	O
PowerPC	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
,	O
Rivina	O
used	O
the	O
complete	O
64-bit	B-Device
PowerPC	B-Architecture
specification	O
including	O
dual	O
precision	O
floating	B-Algorithm
point	I-Algorithm
and	O
address	O
translation	O
.	O
</s>
<s>
guTS	O
had	O
a	O
small	O
single	O
cycle	O
4	O
kB	O
L1	B-General_Concept
cache	I-General_Concept
,	O
and	O
Rivina	O
used	O
a	O
two-cycle	O
,	O
two	O
set	O
associative	O
64	O
kB	O
cache	O
instead	O
.	O
</s>
<s>
The	O
processor	O
comprised	O
over	O
19	O
million	O
transistors	O
,	O
manufactured	O
using	O
IBM	O
's	O
CMOS	B-Device
7S	O
,	O
0.22	O
μm	O
copper	O
fabrication	B-General_Concept
process	I-General_Concept
.	O
</s>
