<s>
The	O
IBM	B-Device
RS64	I-Device
is	O
a	O
family	O
of	O
microprocessors	B-Architecture
used	O
in	O
IBM	O
's	O
RS/6000	B-Device
and	O
AS/400	B-Device
servers	O
in	O
the	O
late	O
1990s	O
.	O
</s>
<s>
These	O
microprocessors	B-Architecture
implement	O
the	O
"	O
Amazon	O
"	O
,	O
or	O
"	O
PowerPC-AS	O
"	O
,	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
Amazon	O
is	O
a	O
superset	O
of	O
the	O
PowerPC	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
,	O
with	O
the	O
addition	O
of	O
special	O
features	O
not	O
in	O
the	O
PowerPC	B-Architecture
specification	O
,	O
mainly	O
derived	O
from	O
POWER2	B-General_Concept
and	O
the	O
original	O
AS/400	B-Device
processor	O
,	O
and	O
has	O
been	O
64-bit	B-Device
from	O
the	O
start	O
.	O
</s>
<s>
The	O
processors	O
in	O
this	O
family	O
are	O
optimized	O
for	O
commercial	O
workloads	O
(	O
integer	O
performance	O
,	O
large	O
caches	O
,	O
branches	O
)	O
and	O
do	O
not	O
feature	O
the	O
strong	O
floating	B-Algorithm
point	I-Algorithm
performance	O
of	O
the	O
processors	O
in	O
the	O
POWER	B-Device
family	O
,	O
its	O
sibling	O
.	O
</s>
<s>
The	O
RS64	B-Device
family	O
was	O
phased	O
out	O
soon	O
after	O
the	O
introduction	O
of	O
the	O
POWER4	B-Device
,	O
which	O
was	O
developed	O
to	O
unite	O
the	O
RS64	B-Device
and	O
POWER	B-Device
families	O
.	O
</s>
<s>
In	O
1990	O
,	O
the	O
AS/400	B-Device
engineering	O
team	O
at	O
IBM	O
Rochester	O
began	O
work	O
on	O
a	O
new	O
architecture	O
known	O
as	O
C-RISC	O
(	O
Commercial	O
RISC	B-Architecture
)	O
to	O
replace	O
the	O
IMPI	O
architecture	O
of	O
the	O
AS/400	B-Device
.	O
</s>
<s>
C-RISC	O
was	O
an	O
evolution	O
of	O
the	O
IMPI	O
instruction	B-General_Concept
set	I-General_Concept
,	O
extending	O
the	O
address	O
space	O
to	O
96	O
bits	O
and	O
adding	O
some	O
RISC	B-Architecture
instructions	O
to	O
speed	O
up	O
the	O
more	O
computationally	O
intensive	O
commercial	O
applications	O
that	O
were	O
being	O
put	O
on	O
AS/400s	B-Device
.	O
</s>
<s>
IBM	O
president	O
Jack	O
Kuehler	O
wanted	O
them	O
to	O
use	O
PowerPC	B-Architecture
,	O
but	O
they	O
resisted	O
,	O
arguing	O
that	O
the	O
existing	O
32/64	O
-bit	O
PowerPC	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
would	O
not	O
enable	O
a	O
viable	O
transition	O
for	O
OS/400	O
software	O
and	O
that	O
the	O
existing	O
instruction	B-General_Concept
set	I-General_Concept
required	O
extensions	O
for	O
the	O
commercial	O
applications	O
on	O
the	O
AS/400	B-Device
.	O
</s>
<s>
At	O
Kuehler	O
's	O
insistence	O
,	O
a	O
team	O
at	O
Rochester	O
led	O
by	O
Frank	O
Soltis	O
investigated	O
the	O
feasibility	O
of	O
extending	O
the	O
PowerPC	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
to	O
support	O
the	O
needs	O
of	O
the	O
AS/400	B-Device
platform	O
.	O
</s>
<s>
These	O
extensions	O
became	O
known	O
as	O
Amazon	O
and	O
were	O
selected	O
by	O
IBM	O
executive	O
management	O
for	O
further	O
development	O
over	O
continued	O
development	O
of	O
C-RISC	O
.	O
</s>
<s>
At	O
the	O
same	O
time	O
,	O
the	O
RS/6000	B-Device
developers	O
were	O
broadly	O
expanding	O
their	O
product	O
line	O
to	O
include	O
systems	O
which	O
spanned	O
from	O
low-end	O
workstations	O
,	O
to	O
mainframe	O
competitor-large	O
enterprise	O
SMP	B-Operating_System
systems	O
,	O
to	O
clustered	O
RS/6000	B-Operating_System
-SP2	I-Operating_System
supercomputing	O
systems	O
.	O
</s>
<s>
PowerPC	B-Architecture
processors	I-Architecture
developed	O
in	O
the	O
AIM	O
alliance	O
suited	O
the	O
low-end	O
RISC	B-Architecture
workstation	O
and	O
small	O
server	B-Application
space	O
well	O
.	O
</s>
<s>
But	O
mainframe	O
and	O
large	O
clustered	O
supercomputing	O
systems	O
required	O
more	O
performance	O
and	O
reliability	B-General_Concept
,	I-General_Concept
availability	I-General_Concept
and	I-General_Concept
serviceability	I-General_Concept
features	O
than	O
processors	O
designed	O
for	O
Apple	O
Power	B-Device
Macs	O
.	O
</s>
<s>
Multiple	O
processor	O
designs	O
were	O
required	O
to	O
simultaneously	O
meet	O
the	O
requirements	O
of	O
the	O
cost-focused	O
Apple	O
Power	B-Device
Mac	O
,	O
high-performance	O
and	O
RAS	O
RS/6000	B-Device
systems	O
,	O
and	O
the	O
AS/400	B-Device
transition	O
to	O
PowerPC	B-Architecture
.	O
</s>
<s>
Amazon	O
was	O
extended	O
to	O
support	O
those	O
features	O
as	O
well	O
,	O
so	O
that	O
processors	O
could	O
be	O
designed	O
for	O
use	O
in	O
both	O
high-end	O
RS/6000	B-Device
and	O
AS/400	B-Device
machines	O
.	O
</s>
<s>
To	O
address	O
technical	O
workstation	O
,	O
supercomputer	O
,	O
and	O
engineering/scientific	O
markets	O
,	O
IBM	O
Austin	O
(	O
the	O
home	O
of	O
the	O
RS/6000s	B-Device
)	O
then	O
started	O
developing	O
a	O
time-to-market	O
single-chip	O
version	O
of	O
the	O
Power2	B-General_Concept
(	O
P2SC	O
)	O
in	O
parallel	O
with	O
the	O
development	O
of	O
a	O
sophisticated	O
64-bit	B-Device
PowerPC	B-Architecture
processor	I-Architecture
with	O
the	O
POWER2	B-General_Concept
extensions	O
and	O
twin	O
sophisticated	O
MAF	O
floating	B-Algorithm
point	I-Algorithm
units	O
(	O
the	O
POWER3/630	O
)	O
.	O
</s>
<s>
To	O
address	O
RS/6000	B-Device
commercial	O
applications	O
and	O
AS/400	B-Device
systems	O
,	O
IBM	O
Rochester	O
(	O
the	O
home	O
of	O
the	O
AS/400s	B-Device
)	O
started	O
developing	O
the	O
first	O
of	O
the	O
high-end	O
64-bit	B-Device
PowerPC	B-Architecture
processors	I-Architecture
with	O
AS/400	B-Device
extensions	O
,	O
and	O
IBM	O
Endicott	O
started	O
developing	O
a	O
low-end	O
single-chip	O
PowerPC	B-Architecture
processor	I-Architecture
with	O
AS/400	B-Device
extensions	O
.	O
</s>
<s>
In	O
1995	O
,	O
IBM	O
released	O
the	O
Cobra	O
,	O
or	O
A10	O
processor	O
,	O
the	O
first	O
full	O
implementation	O
of	O
PowerPC	B-Architecture
AS	O
,	O
for	O
the	O
IBM	B-Device
AS/400	I-Device
systems	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
by	O
IBM	O
in	O
their	O
CMOS	B-Device
5L	O
process	O
,	O
a	O
0.5µm	O
,	O
four-layer-metal	O
CMOS	B-Device
process	O
.	O
</s>
<s>
It	O
used	O
a	O
3.0	O
V	O
power	B-Device
supply	O
and	O
dissipated	O
17.7	O
W	O
maximum	O
,	O
13.4	O
W	O
minimum	O
at	O
77MHz	O
.	O
</s>
<s>
It	O
was	O
packaged	O
in	O
a	O
625-contact	O
ceramic	B-Algorithm
ball	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
CBGA	O
)	O
that	O
measured	O
32mm	O
by	O
32mm	O
.	O
</s>
<s>
Cobra	O
was	O
preceded	O
by	O
a	O
simplified	O
implementation	O
known	O
as	O
Cobra-Lite	O
in	O
1994	O
,	O
which	O
was	O
used	O
in	O
the	O
first	O
IBM	B-Device
Advanced/36	I-Device
systems	O
.	O
</s>
<s>
It	O
lacked	O
17	O
instructions	O
from	O
the	O
full	O
PowerPC	B-Architecture
AS	O
ISA	O
which	O
were	O
not	O
needed	O
for	O
the	O
Advanced/36	B-Device
.	O
</s>
<s>
In	O
1996	O
,	O
IBM	O
released	O
the	O
high-end	O
,	O
4-way	O
SMP	B-Operating_System
,	O
multi-chip	O
version	O
called	O
Muskie	O
,	O
A25	O
or	O
A30	O
in	O
AS/400	B-Device
systems	O
.	O
</s>
<s>
It	O
was	O
manufactured	O
on	O
a	O
BiCMOS	B-General_Concept
fabrication	O
process	O
.	O
</s>
<s>
These	O
processors	O
were	O
only	O
used	O
in	O
AS/400	B-Device
and	O
Advanced/36	B-Device
machines	O
.	O
</s>
<s>
The	O
RS64	B-Device
or	O
Apache	O
was	O
introduced	O
in	O
1997	O
.	O
</s>
<s>
It	O
was	O
developed	O
from	O
"	O
Cobra	O
"	O
and	O
"	O
Muskie	O
"	O
but	O
included	O
a	O
more	O
complete	O
PowerPC	B-Architecture
ISA	O
and	O
was	O
therefore	O
set	O
to	O
be	O
used	O
in	O
RS/6000	B-Device
machines	O
as	O
well	O
as	O
in	O
AS/400	B-Device
systems	O
.	O
</s>
<s>
It	O
scaled	O
to	O
a	O
12	O
processor	O
SMP	B-Operating_System
configuration	O
in	O
IBM	O
's	O
machines	O
.	O
</s>
<s>
RS64	B-Device
was	O
called	O
A35	O
in	O
AS/400	B-Device
and	O
was	O
one	O
time	O
referred	O
to	O
as	O
the	O
PowerPC	B-Architecture
625	O
,	O
between	O
the	O
defunct	O
PowerPC	B-Architecture
620	O
and	O
the	O
PowerPC	B-Architecture
630	O
(	O
later	O
renamed	O
POWER3	B-General_Concept
)	O
.	O
</s>
<s>
It	O
was	O
manufactured	O
with	O
a	O
BiCMOS	B-General_Concept
fabrication	O
process	O
.	O
</s>
<s>
The	O
RS64-II	O
or	O
Northstar	O
was	O
introduced	O
at	O
262MHz	O
in	O
1998	O
with	O
8	O
MB	O
of	O
full	O
speed	O
L2	O
on	O
a	O
256	O
bit	O
6XX	O
bus	O
(	O
also	O
used	O
in	O
PowerPC	B-Architecture
620	O
and	O
POWER3	B-General_Concept
)	O
.	O
</s>
<s>
Processor	O
boards	O
containing	O
4	O
RS64-II	O
'	O
s	O
could	O
be	O
swapped	O
into	O
machines	O
designed	O
for	O
similar	O
4-way	O
RS64	B-Device
boards	O
,	O
avoiding	O
a	O
"	O
fork	O
lift	O
upgrade	O
"	O
.	O
</s>
<s>
The	O
RS64-II	O
contained	O
12.5	O
million	O
transistors	O
,	O
was	O
162mm²	O
large	O
and	O
drew	O
27	O
Watts	O
maximum	O
power	B-Device
.	O
</s>
<s>
Manufacturing	O
changed	O
to	O
a	O
0.35	O
μm	O
CMOS	B-Device
fabrication	O
.	O
</s>
<s>
RS64-II	O
was	O
the	O
first	O
mass-market	O
processor	O
to	O
implement	O
multithreading	B-General_Concept
.	O
</s>
<s>
IBM	O
calls	O
this	O
scheme	O
"	O
coarse	O
grained	O
multithreading	B-General_Concept
"	O
.	O
</s>
<s>
It	O
is	O
not	O
exactly	O
the	O
same	O
thing	O
as	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
as	O
found	O
on	O
later	O
Pentium	B-General_Concept
4	I-General_Concept
processors	O
.	O
</s>
<s>
An	O
IBM	O
paper	O
notes	O
that	O
the	O
coarse	O
grained	O
scheme	O
is	O
a	O
better	O
fit	O
for	O
an	O
in-order	O
architecture	O
like	O
RS64	B-Device
.	O
</s>
<s>
RS64-II	O
was	O
called	O
A50	O
in	O
AS/400	B-Device
systems	O
.	O
</s>
<s>
The	O
RS64-III	O
or	O
Pulsar	O
was	O
introduced	O
in	O
1999	O
at	O
450MHz	O
.	O
</s>
<s>
Key	O
changes	O
included	O
larger	O
128	O
KiB	O
L1	O
instruction	O
and	O
data	O
caches	O
,	O
improved	O
branch	B-General_Concept
prediction	I-General_Concept
accuracy	O
and	O
reduced	O
branch	B-General_Concept
misprediction	I-General_Concept
penalties	O
of	O
zero	O
or	O
one	O
cycle	O
.	O
</s>
<s>
The	O
RS64-III	O
has	O
a	O
five-stage	O
pipeline	O
and	O
a	O
256	O
bit	O
wide	O
L2	O
cache	O
bus	O
,	O
which	O
provided	O
the	O
processor	O
with	O
14.4	O
GB/s	O
of	O
bandwidth	O
from	O
the	O
8	O
MiB	O
L2	O
cache	O
,	O
implemented	O
with	O
225MHz	O
DDR	O
SRAMs	O
.	O
</s>
<s>
The	O
RS64-III	O
has	O
34	O
million	O
transistors	O
,	O
a	O
die	O
size	O
of	O
140mm²	O
,	O
and	O
is	O
manufactured	O
on	O
the	O
0.22	O
μm	O
CMOS	B-Device
7S	O
process	O
with	O
six	O
levels	O
of	O
copper	O
interconnect	O
.	O
</s>
<s>
In	O
2000	O
,	O
IBM	O
launched	O
a	O
refined	O
version	O
called	O
IStar	O
manufactured	O
with	O
a	O
SOI	B-Algorithm
fabrication	O
process	O
with	O
copper	O
interconnects	O
,	O
which	O
increased	O
the	O
processor	O
's	O
clock	O
frequency	O
to	O
600MHz	O
.	O
</s>
<s>
The	O
RS64-IV	O
or	O
Sstar	O
was	O
introduced	O
in	O
2000	O
at	O
600MHz	O
,	O
later	O
increased	O
to	O
750MHz	O
.	O
</s>
<s>
Up	O
to	O
16	O
GB	O
DDR	O
L2	O
was	O
supported	O
in	O
the	O
same	O
manner	O
as	O
the	O
RS64-III	O
(	O
19.2	O
GB/s	O
bandwidth	O
)	O
.	O
</s>
<s>
The	O
RS64-IV	O
had	O
44	O
million	O
transistors	O
and	O
was	O
128mm²	O
large	O
manufactured	O
on	O
a	O
0.18	O
μm	O
process	O
.	O
</s>
<s>
Unlike	O
POWER	B-Device
,	O
energy	O
consumption	O
remained	O
low	O
,	O
at	O
under	O
15	O
watts	O
per	O
core	O
.	O
</s>
<s>
For	O
a	O
time	O
,	O
while	O
the	O
POWER	B-Device
line	O
stagnated	O
at	O
half	O
the	O
clock	O
speed	O
of	O
its	O
competitors	O
,	O
the	O
RS64	B-Device
family	O
was	O
at	O
the	O
top	O
of	O
the	O
IBM	O
large	O
SMP	B-Operating_System
UNIX	O
server	B-Application
line	O
.	O
</s>
<s>
The	O
integer	O
/	O
commercial	O
workload	O
performance	O
of	O
the	O
RS-64	O
IV	O
was	O
similar	O
to	O
the	O
Sun	O
Microsystems	O
processors	O
with	O
which	O
it	O
competed	O
,	O
though	O
its	O
floating	B-Algorithm
point	I-Algorithm
power	B-Device
was	O
not	O
comparable	O
to	O
the	O
contemporary	O
POWER3-II	B-General_Concept
,	O
which	O
remained	O
reasonably	O
competitive	O
throughout	O
its	O
lifecycle	O
.	O
</s>
