<s>
The	O
ROMP	O
is	O
a	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
microprocessor	B-Architecture
designed	O
by	O
IBM	O
in	O
the	O
late	O
1970s	O
.	O
</s>
<s>
It	O
is	O
also	O
known	O
as	O
the	O
Research	O
OPD	B-Protocol
Miniprocessor	I-Protocol
(	O
after	O
the	O
two	O
IBM	O
divisions	O
that	O
collaborated	O
on	O
its	O
inception	O
,	O
IBM	O
Research	O
and	O
the	O
Office	O
Products	O
Division	O
 [ OPD ] 	O
)	O
and	O
032	B-Device
.	O
</s>
<s>
The	O
ROMP	O
was	O
originally	O
developed	O
for	O
office	O
equipment	O
and	O
small	O
computers	O
,	O
intended	O
as	O
a	O
follow-on	O
to	O
the	O
mid-1970s	O
IBM	O
OPD	B-Protocol
Mini	I-Protocol
Processor	I-Protocol
microprocessor	B-Architecture
,	O
which	O
was	O
used	O
in	O
the	O
IBM	B-Protocol
Office	I-Protocol
System/6	I-Protocol
word-processing	O
system	O
.	O
</s>
<s>
The	O
first	O
examples	O
became	O
available	O
in	O
1981	O
,	O
and	O
it	O
was	O
first	O
used	O
commercially	O
in	O
the	O
IBM	B-Device
RT	I-Device
PC	I-Device
announced	O
in	O
January	O
1986	O
.	O
</s>
<s>
For	O
a	O
time	O
,	O
the	O
RT	B-Device
PC	I-Device
was	O
planned	O
to	O
be	O
a	O
personal	B-Device
computer	I-Device
,	O
with	O
ROMP	O
replacing	O
the	O
Intel	B-Device
8088	I-Device
found	O
in	O
the	O
IBM	B-Device
Personal	I-Device
Computer	I-Device
.	O
</s>
<s>
However	O
,	O
the	O
RT	B-Device
PC	I-Device
was	O
later	O
repositioned	O
as	O
an	O
engineering	O
and	O
scientific	O
workstation	B-Device
computer	I-Device
.	O
</s>
<s>
A	O
later	O
CMOS	B-Device
version	O
of	O
the	O
ROMP	O
was	O
first	O
used	O
in	O
the	O
coprocessor	B-General_Concept
board	O
for	O
the	O
IBM	B-Device
6152	I-Device
Academic	I-Device
System	I-Device
introduced	O
in	O
1988	O
,	O
and	O
it	O
later	O
appeared	O
in	O
some	O
models	O
of	O
the	O
RT	B-Device
PC	I-Device
.	O
</s>
<s>
The	O
architectural	B-General_Concept
work	O
on	O
the	O
ROMP	O
began	O
in	O
late	O
spring	O
of	O
1977	O
,	O
as	O
a	O
spin-off	O
of	O
IBM	O
Research	O
's	O
801	B-Device
RISC	B-Architecture
processor	I-Architecture
(	O
hence	O
the	O
"	O
Research	O
"	O
in	O
the	O
acronym	O
)	O
.	O
</s>
<s>
Most	O
of	O
the	O
architectural	B-General_Concept
changes	O
were	O
for	O
cost	O
reduction	O
,	O
such	O
as	O
adding	O
16-bit	O
instructions	O
for	O
byte-efficiency	O
.	O
</s>
<s>
The	O
original	O
ROMP	O
had	O
a	O
24-bit	O
architecture	O
,	O
but	O
the	O
instruction	B-General_Concept
set	I-General_Concept
was	O
changed	O
to	O
32	O
bits	O
a	O
few	O
years	O
into	O
the	O
development	O
.	O
</s>
<s>
The	O
first	O
chips	O
were	O
ready	O
in	O
early	O
1981	O
,	O
making	O
ROMP	O
the	O
first	O
industrial	O
RISC	B-Architecture
.	O
</s>
<s>
The	O
processor	O
was	O
revealed	O
at	O
the	O
International	O
Solid-State	O
Circuits	O
Conference	O
in	O
1984	O
ROMP	O
first	O
appeared	O
in	O
a	O
commercial	O
product	O
as	O
the	O
processor	O
for	O
the	O
IBM	B-Device
RT	I-Device
PC	I-Device
workstation	B-Device
,	O
which	O
was	O
introduced	O
in	O
1986	O
.	O
</s>
<s>
To	O
provide	O
examples	O
for	O
RT	B-Device
PC	I-Device
production	O
,	O
volume	O
production	O
of	O
the	O
ROMP	O
and	O
its	O
MMU	O
began	O
in	O
1985	O
.	O
</s>
<s>
The	O
delay	O
between	O
the	O
completion	O
of	O
the	O
ROMP	O
design	O
,	O
and	O
introduction	O
of	O
the	O
RT	B-Device
PC	I-Device
was	O
caused	O
by	O
overly	O
ambitious	O
software	O
plans	O
for	O
the	O
RT	B-Device
PC	I-Device
and	O
its	O
operating	B-General_Concept
system	I-General_Concept
(	O
OS	O
)	O
.	O
</s>
<s>
This	O
OS	O
virtualized	O
the	O
hardware	O
and	O
could	O
host	O
multiple	O
other	O
operating	B-General_Concept
systems	I-General_Concept
.	O
</s>
<s>
This	O
technology	O
,	O
called	O
virtualization	B-General_Concept
,	O
while	O
commonplace	O
in	O
mainframe	B-Architecture
systems	O
,	O
only	O
began	O
to	O
gain	O
traction	O
in	O
smaller	O
systems	O
in	O
the	O
21st	O
century	O
.	O
</s>
<s>
An	O
improved	O
CMOS	B-Device
version	O
of	O
the	O
ROMP	O
was	O
first	O
used	O
in	O
the	O
IBM	B-Device
6152	I-Device
Academic	I-Device
System	I-Device
workstation	B-Device
,	O
and	O
later	O
in	O
some	O
models	O
of	O
the	O
RT	B-Device
PC	I-Device
.	O
</s>
<s>
IBM	O
Research	O
used	O
the	O
ROMP	O
in	O
its	O
Research	O
Parallel	O
Processor	O
Prototype	O
(	O
RP3	O
)	O
,	O
an	O
early	O
experimental	O
scalable	O
shared-memory	B-Operating_System
multiprocessor	I-Operating_System
that	O
supported	O
up	O
to	O
512	O
processors	O
first	O
detailed	O
in	O
1985	O
;	O
and	O
the	O
CMOS	B-Device
version	O
in	O
its	O
ACE	O
,	O
an	O
experimental	O
NUMA	O
multiprocessor	O
that	O
was	O
operational	O
in	O
1988	O
.	O
</s>
<s>
The	O
ROMP	O
's	O
architecture	O
was	O
based	O
on	O
the	O
original	O
version	O
of	O
the	O
IBM	O
Research	O
801	B-Device
minicomputer	B-Architecture
.	O
</s>
<s>
The	O
main	O
differences	O
were	O
a	O
larger	O
word	O
size	O
(	O
32	O
bits	O
instead	O
of	O
24	O
)	O
,	O
and	O
the	O
inclusion	O
of	O
virtual	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
The	O
architecture	O
supported	O
8-	O
,	O
16-	O
,	O
and	O
32-bit	O
integers	O
,	O
32-bit	O
addressing	O
,	O
and	O
a	O
40-bit	O
virtual	B-General_Concept
address	I-General_Concept
space	I-General_Concept
.	O
</s>
<s>
It	O
had	O
an	O
instruction	B-General_Concept
pointer	I-General_Concept
register	I-General_Concept
and	O
sixteen	O
32-bit	O
general-purpose	O
registers	O
.	O
</s>
<s>
The	O
microprocessor	B-Architecture
was	O
controlled	O
by	O
118	O
simple	O
16	O
-	O
and	O
32-bit	O
instructions	O
.	O
</s>
<s>
The	O
ROMP	O
's	O
virtual	B-Architecture
memory	I-Architecture
has	O
a	O
segmented	B-General_Concept
40-bit	O
(	O
1TB	O
)	O
address	O
space	O
consisting	O
of	O
4,096	O
256MB	O
segments	O
.	O
</s>
<s>
The	O
40-bit	O
virtual	B-General_Concept
address	I-General_Concept
is	O
formed	O
in	O
the	O
MMU	O
by	O
concatenating	O
a	O
12-bit	O
segment	O
identifier	O
with	O
28	O
low-order	O
bits	O
from	O
a	O
32-bit	O
ROMP-computed	O
virtual	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
The	O
segment	O
identifier	O
is	O
obtained	O
from	O
a	O
set	O
of	O
16	O
segment	O
identifiers	O
stored	O
in	O
the	O
MMU	O
,	O
addressed	O
by	O
the	O
four	O
high-order	O
bits	O
of	O
the	O
32-bit	O
ROMP-computed	O
virtual	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
The	O
ROMP	O
is	O
a	O
scalar	B-General_Concept
processor	I-General_Concept
with	O
a	O
three-stage	O
pipeline	O
.	O
</s>
<s>
Rosetta	O
was	O
a	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
,	O
and	O
it	O
provided	O
the	O
ROMP	O
with	O
address	O
translation	O
facilities	O
,	O
a	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
,	O
and	O
a	O
store	O
buffer	O
.	O
</s>
<s>
Both	O
are	O
packaged	O
in	O
135-pin	O
ceramic	B-Algorithm
pin	I-Algorithm
grid	I-Algorithm
arrays	I-Algorithm
.	O
</s>
<s>
A	O
CMOS	B-Device
version	O
of	O
the	O
ROMP	O
and	O
Rosetta	O
(	O
called	O
ROMP-C	O
and	O
Rosetta-C	O
)	O
was	O
later	O
developed	O
.	O
</s>
