<s>
IBM	B-Device
Power	I-Device
microprocessors	I-Device
(	O
originally	O
POWER	B-Architecture
prior	O
to	O
Power10	B-Operating_System
)	O
are	O
designed	O
and	O
sold	O
by	O
IBM	O
for	O
servers	B-Application
and	O
supercomputers	B-Architecture
.	O
</s>
<s>
The	O
name	O
"	O
POWER	B-Architecture
"	O
was	O
originally	O
presented	O
as	O
an	O
acronym	O
for	O
"	O
Performance	O
Optimization	O
With	O
Enhanced	O
RISC	B-Architecture
"	O
.	O
</s>
<s>
The	O
Power	B-Architecture
line	O
of	O
microprocessors	B-Architecture
has	O
been	O
used	O
in	O
IBM	O
's	O
RS/6000	B-Device
,	O
AS/400	B-Device
,	O
pSeries	O
,	O
iSeries	B-Device
,	O
System	B-Device
p	I-Device
,	O
System	B-Device
i	I-Device
,	O
and	O
Power	B-Device
Systems	I-Device
lines	O
of	O
servers	B-Application
and	O
supercomputers	B-Architecture
.	O
</s>
<s>
They	O
have	O
also	O
been	O
used	O
in	O
data	B-General_Concept
storage	I-General_Concept
devices	I-General_Concept
and	O
workstations	B-Device
by	O
IBM	O
and	O
by	O
other	O
server	O
manufacturers	O
like	O
Bull	O
and	O
Hitachi	O
.	O
</s>
<s>
The	O
Power	B-Architecture
family	O
was	O
originally	O
developed	O
in	O
the	O
late	O
1980s	O
,	O
and	O
remains	O
under	O
active	O
development	O
.	O
</s>
<s>
In	O
the	O
beginning	O
,	O
they	O
implemented	O
the	O
POWER	B-Architecture
instruction	I-Architecture
set	I-Architecture
architecture	I-Architecture
(	O
ISA	O
)	O
,	O
which	O
evolved	O
into	O
PowerPC	B-Architecture
and	O
later	O
into	O
Power	B-Architecture
ISA	I-Architecture
.	O
</s>
<s>
In	O
August	O
2019	O
,	O
IBM	O
announced	O
it	O
would	O
open	B-License
source	I-License
the	O
Power	B-Architecture
ISA	I-Architecture
.	O
</s>
<s>
As	O
part	O
of	O
the	O
move	O
,	O
it	O
was	O
also	O
announced	O
that	O
administration	O
of	O
the	O
OpenPOWER	B-Application
Foundation	I-Application
will	O
now	O
be	O
handled	O
by	O
the	B-Operating_System
Linux	I-Operating_System
Foundation	I-Operating_System
.	O
</s>
<s>
In	O
1974	O
IBM	O
started	O
a	O
project	O
to	O
build	O
a	O
telephone	O
switching	O
computer	O
that	O
required	O
,	O
for	O
the	O
time	O
,	O
immense	O
computational	O
power	B-Architecture
.	O
</s>
<s>
Since	O
the	O
application	O
was	O
comparably	O
simple	O
,	O
this	O
machine	O
would	O
need	O
only	O
to	O
perform	O
I/O	B-General_Concept
,	O
branches	B-General_Concept
,	O
add	O
register-register	B-General_Concept
,	O
move	O
data	O
between	O
registers	O
and	O
memory	B-Architecture
,	O
and	O
would	O
have	O
no	O
need	O
for	O
special	O
instructions	O
to	O
perform	O
heavy	O
arithmetic	O
.	O
</s>
<s>
This	O
simple	O
design	O
philosophy	O
,	O
whereby	O
each	O
step	O
of	O
a	O
complex	O
operation	O
is	O
specified	O
explicitly	O
by	O
one	O
machine	O
instruction	O
,	O
and	O
all	O
instructions	O
are	O
required	O
to	O
complete	O
in	O
the	O
same	O
constant	O
time	O
,	O
would	O
later	O
come	O
to	O
be	O
known	O
as	O
RISC	B-Architecture
.	O
</s>
<s>
By	O
1982	O
IBM	O
continued	O
to	O
explore	O
the	O
superscalar	B-General_Concept
limits	O
of	O
the	O
801	O
design	O
by	O
using	O
multiple	O
execution	B-General_Concept
units	I-General_Concept
to	O
improve	O
performance	O
to	O
determine	O
if	O
a	O
RISC	B-Architecture
machine	O
could	O
maintain	O
multiple	O
instructions	O
per	O
cycle	O
.	O
</s>
<s>
Many	O
changes	O
were	O
made	O
to	O
the	O
801	O
design	O
to	O
allow	O
for	O
multiple	O
execution	B-General_Concept
units	I-General_Concept
and	O
the	O
Cheetah	O
processor	O
has	O
separate	O
units	O
for	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
fixed-point	B-General_Concept
,	O
and	O
floating-point	B-General_Concept
execution	O
.	O
</s>
<s>
By	O
1984	O
CMOS	B-Device
was	O
chosen	O
because	O
it	O
allows	O
improved	O
circuit	O
integration	O
and	O
transistor-logic	O
performance	O
.	O
</s>
<s>
In	O
1985	O
,	O
research	O
on	O
a	O
second-generation	O
RISC	B-Architecture
architecture	O
started	O
at	O
the	O
IBM	O
Thomas	O
J	O
.	O
Watson	O
Research	O
Center	O
,	O
producing	O
the	O
"	O
AMERICA	O
architecture	O
"	O
.	O
</s>
<s>
In	O
1986	O
,	O
IBM	O
Austin	O
started	O
developing	O
the	O
RS/6000	B-Device
series	O
computers	O
based	O
on	O
that	O
architecture	O
.	O
</s>
<s>
This	O
was	O
to	O
become	O
the	O
first	O
POWER	B-Architecture
processors	O
using	O
the	O
first	O
POWER	B-Architecture
ISA	I-Architecture
.	O
</s>
<s>
The	O
first	O
IBM	O
computers	O
to	O
incorporate	O
the	O
POWER	B-Architecture
ISA	I-Architecture
are	O
the	O
RISC	B-Device
System/6000	I-Device
or	O
RS/6000	B-Device
series	O
.	O
</s>
<s>
These	O
RS/6000	B-Device
computers	O
were	O
divided	O
into	O
two	O
classes	O
,	O
POWERstation	O
workstations	B-Device
and	O
POWERserver	O
servers	B-Application
.	O
</s>
<s>
The	O
first	O
RS/6000	B-Device
CPU	O
has	O
2	O
configurations	O
,	O
called	O
the	O
"	O
RIOS-1	B-General_Concept
"	O
and	O
"	O
RIOS.9	O
"	O
(	O
or	O
more	O
commonly	O
the	O
POWER1	B-General_Concept
CPU	O
)	O
.	O
</s>
<s>
A	O
RIOS-1	B-General_Concept
configuration	O
has	O
a	O
total	O
of	O
10	O
discrete	O
chips	O
:	O
an	O
instruction	O
cache	O
chip	O
,	O
fixed-point	B-General_Concept
chip	O
,	O
floating-point	B-General_Concept
chip	O
,	O
4	O
data	B-General_Concept
L1	I-General_Concept
cache	I-General_Concept
chips	O
,	O
storage	O
control	O
chip	O
,	O
input/output	B-General_Concept
chips	O
,	O
and	O
a	O
clock	O
chip	O
.	O
</s>
<s>
The	O
lower	O
cost	O
RIOS.9	O
configuration	O
has	O
8	O
discrete	O
chips	O
:	O
an	O
instruction	O
cache	O
chip	O
,	O
fixed-point	B-General_Concept
chip	O
,	O
floating-point	B-General_Concept
chip	O
,	O
2	O
data	B-General_Concept
cache	I-General_Concept
chips	O
,	O
storage	O
control	O
chip	O
,	O
input/output	B-General_Concept
chip	O
,	O
and	O
a	O
clock	O
chip	O
.	O
</s>
<s>
The	O
POWER1	B-General_Concept
is	O
the	O
first	O
microprocessor	B-Architecture
that	O
used	O
register	B-Architecture
renaming	I-Architecture
and	O
out-of-order	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
A	O
simplified	O
and	O
less	O
powerful	O
version	O
of	O
the	O
10	O
chip	O
RIOS-1	B-General_Concept
was	O
made	O
in	O
1992	O
,	O
for	O
lower-end	O
RS/6000s	B-Device
.	O
</s>
<s>
It	O
uses	O
only	O
one	O
chip	O
and	O
is	O
called	O
RISC	B-Device
Single	I-Device
Chip	I-Device
or	O
RSC	B-Device
.	O
</s>
<s>
IBM	O
started	O
the	O
POWER2	B-General_Concept
processor	O
effort	O
as	O
a	O
successor	O
to	O
the	O
POWER1	B-General_Concept
.	O
</s>
<s>
By	O
adding	O
a	O
second	O
fixed-point	B-General_Concept
unit	O
,	O
a	O
second	O
powerful	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
,	O
and	O
other	O
performance	O
enhancements	O
and	O
new	O
instructions	O
to	O
the	O
design	O
,	O
the	O
POWER2	B-General_Concept
ISA	O
had	O
leadership	O
performance	O
when	O
it	O
was	O
announced	O
in	O
November	O
1993	O
.	O
</s>
<s>
The	O
POWER2	B-General_Concept
was	O
a	O
multi-chip	O
design	O
,	O
but	O
IBM	O
also	O
made	O
a	O
single	O
chip	O
design	O
of	O
it	O
,	O
called	O
the	O
POWER2	B-General_Concept
Super	O
Chip	O
or	O
P2SC	O
that	O
went	O
into	O
high	O
performance	O
servers	B-Application
and	O
supercomputers	B-Architecture
.	O
</s>
<s>
In	O
1991	O
,	O
Apple	O
looked	O
for	O
a	O
future	O
alternative	O
to	O
the	O
CISC-based	O
Motorola	B-Device
68000	I-Device
series	I-Device
platform	O
,	O
and	O
Motorola	O
experimented	O
with	O
a	O
RISC	B-Architecture
platform	O
of	O
its	O
own	O
,	O
the	O
88000	B-Architecture
.	O
</s>
<s>
IBM	O
joined	O
the	O
discussion	O
and	O
the	O
three	O
founded	O
the	O
AIM	O
alliance	O
to	O
build	O
the	O
PowerPC	B-Architecture
ISA	O
,	O
heavily	O
based	O
on	O
the	O
POWER	B-Architecture
ISA	I-Architecture
,	O
but	O
with	O
additions	O
from	O
both	O
Apple	O
and	O
Motorola	O
.	O
</s>
<s>
It	O
was	O
to	O
be	O
a	O
complete	O
32/64	O
bit	O
RISC	B-Architecture
architecture	O
,	O
and	O
to	O
range	O
from	O
very	O
low	O
end	O
embedded	B-Architecture
microcontrollers	B-Architecture
to	O
the	O
very	O
high	O
end	O
supercomputer	B-Architecture
and	O
server	B-Application
applications	I-Application
.	O
</s>
<s>
After	O
two	O
years	O
of	O
development	O
,	O
the	O
resulting	O
PowerPC	B-Architecture
ISA	O
was	O
introduced	O
in	O
1993	O
.	O
</s>
<s>
A	O
modified	O
version	O
of	O
the	O
RSC	B-Device
architecture	O
,	O
PowerPC	B-Architecture
added	O
single-precision	O
floating	O
point	O
instructions	O
and	O
general	O
register-to-register	O
multiply	O
and	O
divide	O
instructions	O
,	O
and	O
removed	O
some	O
POWER	B-Architecture
features	O
.	O
</s>
<s>
It	O
also	O
added	O
a	O
64-bit	O
version	O
of	O
the	O
ISA	O
and	O
support	O
for	O
SMP	B-Operating_System
.	O
</s>
<s>
In	O
1990	O
,	O
IBM	O
wanted	O
to	O
merge	O
the	O
low	O
end	O
server	O
and	O
mid	O
range	O
server	O
architectures	O
,	O
the	O
RS/6000	B-Device
RISC	B-Architecture
ISA	O
and	O
AS/400	B-Device
CISC	B-Architecture
ISA	O
into	O
one	O
common	O
RISC	B-Architecture
ISA	O
that	O
could	O
host	O
both	O
IBM	O
's	O
AIX	B-Application
and	O
OS/400	B-Application
operating	O
systems	O
.	O
</s>
<s>
The	O
existing	O
POWER	B-Architecture
and	O
the	O
upcoming	O
PowerPC	B-Architecture
ISAs	B-General_Concept
were	O
deemed	O
unsuitable	O
by	O
the	O
AS/400	B-Device
team	O
so	O
an	O
extension	O
to	O
the	O
64-bit	O
PowerPC	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
was	O
developed	O
called	O
PowerPC	B-Architecture
AS	O
for	O
Advances	O
Series	O
or	O
Amazon	O
Series	O
.	O
</s>
<s>
Later	O
,	O
additions	O
from	O
the	O
RS/6000	B-Device
team	O
and	O
AIM	O
Alliance	O
PowerPC	B-Architecture
were	O
included	O
,	O
and	O
by	O
2001	O
,	O
with	O
the	O
introduction	O
of	O
POWER4	B-Device
,	O
they	O
were	O
all	O
joined	O
into	O
one	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
:	O
the	O
PowerPC	B-Architecture
v.2.0	O
.	O
</s>
<s>
The	O
POWER3	B-General_Concept
began	O
as	O
PowerPC	B-Architecture
630	O
,	O
a	O
successor	O
of	O
the	O
commercially	O
unsuccessful	O
PowerPC	B-Architecture
620	O
.	O
</s>
<s>
It	O
uses	O
a	O
combination	O
of	O
the	O
POWER2	B-General_Concept
ISA	O
and	O
the	O
32/64	O
-bit	O
PowerPC	B-Architecture
ISA	O
set	O
with	O
support	O
for	O
SMP	B-Operating_System
and	O
single-chip	O
implementation	O
.	O
</s>
<s>
It	O
was	O
used	O
to	O
great	O
extent	O
in	O
IBM	O
's	O
RS/6000	B-Device
computers	O
,	O
and	O
the	O
second	O
generation	O
version	O
,	O
the	O
POWER3-II	O
,	O
is	O
the	O
first	O
commercially	O
available	O
processor	O
from	O
IBM	O
using	O
copper	O
interconnects	O
.	O
</s>
<s>
The	O
POWER3	B-General_Concept
is	O
the	O
last	O
processor	O
to	O
use	O
a	O
POWER	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
,	O
and	O
all	O
subsequent	O
models	O
use	O
the	O
PowerPC	B-Architecture
instruction	B-General_Concept
sets	I-General_Concept
.	O
</s>
<s>
POWER3	B-General_Concept
–	O
Introduced	O
in	O
1998	O
,	O
it	O
combined	O
the	O
POWER	B-Architecture
and	O
PowerPC	B-Architecture
instruction	B-General_Concept
sets	I-General_Concept
.	O
</s>
<s>
POWER3-II	O
–	O
A	O
faster	O
POWER3	B-General_Concept
fabricated	O
on	O
a	O
reduced	O
size	O
,	O
copper	O
based	O
process	O
.	O
</s>
<s>
The	O
POWER4	B-Device
merged	O
the	O
32/64	O
bit	O
PowerPC	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
and	O
the	O
64-bit	O
PowerPC	B-Architecture
AS	O
instruction	B-General_Concept
set	I-General_Concept
from	O
the	O
Amazon	O
project	O
to	O
the	O
new	O
PowerPC	B-Architecture
v.2.0	O
specification	O
,	O
unifying	O
IBM	O
's	O
RS/6000	B-Device
and	O
AS/400	B-Device
families	O
of	O
computers	O
.	O
</s>
<s>
Besides	O
the	O
unification	O
of	O
the	O
different	O
platforms	O
,	O
POWER4	B-Device
was	O
also	O
designed	O
to	O
reach	O
very	O
high	O
frequencies	O
and	O
have	O
large	O
on-die	O
L2	O
caches	O
.	O
</s>
<s>
It	O
is	O
the	O
first	O
commercially	O
available	O
multi-core	B-Architecture
processor	I-Architecture
and	O
came	O
in	O
single-die	O
versions	O
as	O
well	O
as	O
in	O
four-chip	O
multi-chip	B-Algorithm
modules	I-Algorithm
.	O
</s>
<s>
In	O
2002	O
,	O
IBM	O
also	O
made	O
a	O
cost	O
-	O
and	O
feature-reduced	O
version	O
of	O
the	O
POWER4	B-Device
called	O
PowerPC	B-General_Concept
970	I-General_Concept
by	O
Apple	O
's	O
request	O
.	O
</s>
<s>
POWER4	B-Device
–	O
The	O
first	O
dual	B-Architecture
core	I-Architecture
microprocessor	B-Architecture
and	O
the	O
first	O
PowerPC	B-Architecture
processor	I-Architecture
to	O
reach	O
beyond	O
1GHz	O
.	O
</s>
<s>
POWER4+	B-Device
–	O
A	O
faster	O
POWER4	B-Device
fabricated	O
on	O
a	O
reduced	O
process	O
.	O
</s>
<s>
The	O
POWER5	B-Device
processors	O
built	O
on	O
the	O
popular	O
POWER4	B-Device
and	O
incorporated	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
into	O
the	O
design	O
,	O
a	O
technology	O
pioneered	O
in	O
the	O
PowerPC	B-Architecture
AS	O
based	O
RS64-III	O
processor	O
,	O
and	O
on-die	O
memory	B-General_Concept
controllers	I-General_Concept
.	O
</s>
<s>
It	O
was	O
designed	O
for	O
multiprocessing	O
on	O
a	O
massive	O
scale	O
and	O
came	O
in	O
multi-chip	B-Algorithm
modules	I-Algorithm
with	O
onboard	O
large	O
L3	O
cache	O
chips	O
.	O
</s>
<s>
POWER5	B-Device
–	O
The	O
iconic	O
setup	O
with	O
four	O
POWER5	B-Device
chips	O
and	O
four	O
L3	O
cache	O
chips	O
on	O
a	O
large	O
multi-chip	B-Algorithm
module	I-Algorithm
.	O
</s>
<s>
POWER5+	O
–	O
A	O
faster	O
POWER5	B-Device
fabricated	O
on	O
a	O
reduced	O
process	O
mainly	O
to	O
reduce	O
power	B-Architecture
consumption	O
.	O
</s>
<s>
A	O
joint	O
organization	O
was	O
founded	O
in	O
2004	O
called	O
Power.org	O
with	O
the	O
mission	O
to	O
unify	O
and	O
coordinate	O
future	O
development	O
of	O
the	O
PowerPC	B-Architecture
specifications	O
.	O
</s>
<s>
By	O
then	O
,	O
the	O
PowerPC	B-Architecture
specification	O
was	O
fragmented	O
since	O
Freescale	O
(	O
née	O
Motorola	O
)	O
and	O
IBM	O
had	O
taken	O
different	O
paths	O
in	O
their	O
respective	O
development	O
of	O
it	O
.	O
</s>
<s>
Freescale	O
had	O
prioritized	O
32-bit	O
embedded	B-Architecture
applications	O
and	O
IBM	O
high-end	O
servers	B-Application
and	O
supercomputers	B-Architecture
.	O
</s>
<s>
The	O
new	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
was	O
called	O
Power	B-Architecture
ISA	I-Architecture
and	O
merged	O
the	O
PowerPC	B-Architecture
v.2.02	O
from	O
the	O
POWER5	B-Device
with	O
the	O
PowerPC	B-Architecture
Book	O
E	O
specification	O
from	O
Freescale	O
as	O
well	O
as	O
some	O
related	O
technologies	O
like	O
the	O
Vector-Media	O
Extensions	O
known	O
under	O
the	O
brand	O
name	O
AltiVec	B-General_Concept
(	O
also	O
called	O
VMX	O
by	O
IBM	O
)	O
and	O
hardware	B-General_Concept
virtualization	I-General_Concept
.	O
</s>
<s>
This	O
new	O
ISA	O
was	O
called	O
'	O
Power	B-Architecture
ISA	I-Architecture
v.2.03	O
and	O
POWER6	B-Device
was	O
the	O
first	O
high	O
end	O
processor	O
from	O
IBM	O
to	O
use	O
it	O
.	O
</s>
<s>
Older	O
POWER	B-Architecture
and	O
PowerPC	B-Architecture
specifications	O
did	O
not	O
make	O
the	O
cut	O
and	O
those	O
instruction	B-General_Concept
sets	I-General_Concept
were	O
henceforth	O
deprecated	B-General_Concept
for	O
good	O
.	O
</s>
<s>
There	O
is	O
no	O
active	O
development	O
on	O
any	O
processor	O
type	O
today	O
that	O
uses	O
these	O
older	O
instruction	B-General_Concept
sets	I-General_Concept
.	O
</s>
<s>
POWER6	B-Device
was	O
the	O
fruit	O
of	O
the	O
ambitious	O
eCLipz	B-Device
Project	I-Device
,	O
joining	O
the	O
I	O
(	O
AS/400	B-Device
)	O
,	O
P	O
(	O
RS/6000	B-Device
)	O
and	O
Z	O
(	O
Mainframe	O
)	O
instruction	B-General_Concept
sets	I-General_Concept
under	O
one	O
common	O
platform	O
.	O
</s>
<s>
I	O
and	O
P	O
was	O
already	O
joined	O
with	O
the	O
POWER4	B-Device
,	O
but	O
the	O
eCLipz	B-Device
effort	O
failed	O
to	O
include	O
the	O
CISC	B-Architecture
based	O
z/Architecture	B-Device
and	O
where	O
the	O
z10	B-Device
processor	I-Device
became	O
POWER6	B-Device
's	O
eCLipz	B-Device
sibling	O
.	O
</s>
<s>
,	O
a	O
separate	O
line	O
of	O
processors	O
implementing	O
z/Architecture	B-Device
continue	O
to	O
be	O
developed	O
by	O
IBM	O
,	O
with	O
the	O
latest	O
being	O
the	O
IBM	B-Device
Telum	I-Device
.	O
</s>
<s>
Because	O
of	O
eCLipz	B-Device
,	O
the	O
POWER6	B-Device
is	O
an	O
unusual	O
design	O
as	O
it	O
aimed	O
for	O
very	O
high	O
frequencies	O
and	O
sacrificed	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
something	O
that	O
has	O
been	O
a	O
feature	O
for	O
POWER	B-Architecture
and	O
PowerPC	B-Architecture
processors	I-Architecture
since	O
their	O
inception	O
.	O
</s>
<s>
POWER6	B-Device
also	O
introduced	O
the	O
decimal	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
to	O
the	O
Power	B-Architecture
ISA	I-Architecture
,	O
something	O
it	O
shares	O
with	O
z/Architecture	B-Device
.	O
</s>
<s>
With	O
the	O
POWER6	B-Device
,	O
in	O
2008	O
IBM	O
merged	O
the	O
former	O
System	B-Device
p	I-Device
and	O
System	B-Device
i	I-Device
server	O
and	O
workstation	B-Device
families	O
into	O
one	O
family	O
called	O
Power	B-Device
Systems	I-Device
.	O
</s>
<s>
Power	B-Device
Systems	I-Device
machines	O
can	O
run	O
different	O
operating	O
systems	O
like	O
AIX	B-Application
,	O
Linux	B-Operating_System
,	O
and	O
IBM	B-Application
i	I-Application
.	O
</s>
<s>
POWER6	B-Device
–	O
Reached	O
5GHz	O
;	O
comes	O
in	O
modules	O
with	O
a	O
single	O
chip	O
on	O
it	O
,	O
and	O
in	O
MCM	O
with	O
two	O
L3	O
cache	O
chips	O
.	O
</s>
<s>
POWER6+	O
–	O
A	O
minor	O
update	O
,	O
fabricated	O
on	O
the	O
same	O
process	O
as	O
POWER6	B-Device
.	O
</s>
<s>
The	O
POWER7	B-Device
symmetric	B-Operating_System
multiprocessor	I-Operating_System
design	O
was	O
a	O
substantial	O
evolution	O
from	O
the	O
POWER6	B-Device
design	O
,	O
focusing	O
more	O
on	O
power	B-Architecture
efficiency	O
through	O
multiple	O
cores	O
,	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
and	O
large	O
on-die	O
eDRAM	O
L3	O
caches	O
.	O
</s>
<s>
It	O
uses	O
a	O
new	O
high-performance	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
called	O
VSX	O
that	O
merges	O
the	O
functionality	O
of	O
the	O
traditional	O
FPU	O
with	O
AltiVec	B-General_Concept
.	O
</s>
<s>
Even	O
while	O
the	O
POWER7	B-Device
run	O
at	O
lower	O
frequencies	O
than	O
POWER6	B-Device
,	O
each	O
POWER7	B-Device
core	O
performs	O
faster	O
than	O
its	O
POWER6	B-Device
counterpart	O
.	O
</s>
<s>
POWER7	B-Device
–	O
Comes	O
in	O
single-chip	O
modules	O
or	O
in	O
quad-chip	O
MCM-configurations	O
for	O
supercomputer	B-Architecture
applications	O
.	O
</s>
<s>
POWER7+	O
–	O
Scaled	O
down	O
fabrication	O
process	O
,	O
and	O
increased	O
L3	O
cache	O
and	O
frequency	O
.	O
</s>
<s>
POWER8	B-Device
is	O
a	O
4GHz	O
,	O
12	O
core	O
processor	O
with	O
8	O
hardware	O
threads	O
per	O
core	O
for	O
a	O
total	O
of	O
96	O
threads	O
of	O
parallel	O
execution	O
.	O
</s>
<s>
The	O
CAPI	O
bus	O
can	O
be	O
used	O
to	O
attach	O
dedicated	O
off-chip	O
accelerator	O
chips	O
such	O
as	O
GPUs	B-Architecture
,	O
ASICs	O
and	O
FPGAs	B-Architecture
.	O
</s>
<s>
IBM	O
states	O
that	O
it	O
is	O
two	O
to	O
three	O
times	O
as	O
fast	O
as	O
its	O
predecessor	O
,	O
the	O
POWER7	B-Device
.	O
</s>
<s>
It	O
was	O
first	O
built	O
on	O
a	O
22	B-Algorithm
nanometer	I-Algorithm
process	O
in	O
2014	O
.	O
</s>
<s>
In	O
December	O
2012	O
,	O
IBM	O
began	O
submitting	O
patches	O
to	O
the	O
3.8	O
version	O
of	O
the	O
Linux	B-Operating_System
kernel	I-Operating_System
,	O
to	O
support	O
new	O
POWER8	B-Device
features	O
including	O
the	O
VSX-2	O
instructions	O
.	O
</s>
<s>
IBM	O
spent	O
much	O
time	O
designing	O
the	O
POWER9	B-Device
processor	O
according	O
to	O
William	O
Starke	O
,	O
a	O
systems	O
architect	O
for	O
the	O
POWER8	B-Device
processor	O
.	O
</s>
<s>
The	O
POWER9	B-Device
is	O
the	O
first	O
to	O
incorporate	O
elements	O
of	O
the	O
Power	B-Architecture
ISA	I-Architecture
version	O
3.0	O
that	O
was	O
released	O
in	O
December	O
2015	O
,	O
including	O
the	O
VSX-3	O
instructions	O
,	O
and	O
also	O
incorporates	O
support	O
for	O
Nvidia	O
's	O
NVLink	O
bus	O
technology	O
.	O
</s>
<s>
The	O
United	O
States	O
Department	O
of	O
Energy	O
together	O
with	O
Oak	O
Ridge	O
National	O
Laboratory	O
and	O
Lawrence	O
Livermore	O
National	O
Laboratory	O
contracted	O
IBM	O
and	O
Nvidia	O
to	O
build	O
two	O
supercomputers	B-Architecture
,	O
the	O
Sierra	O
and	O
the	O
Summit	O
,	O
based	O
on	O
POWER9	B-Device
processors	O
coupled	O
with	O
Nvidia	O
's	O
Volta	O
GPUs	B-Architecture
.	O
</s>
<s>
POWER9	B-Device
,	O
which	O
was	O
launched	O
in	O
2017	O
,	O
is	O
manufactured	O
using	O
a	O
14	B-Algorithm
nm	I-Algorithm
FinFET	O
process	O
,	O
and	O
comes	O
in	O
four	O
versions	O
,	O
two	O
24	O
core	O
SMT4	O
versions	O
intended	O
to	O
use	O
PowerNV	O
for	O
scale	O
up	O
and	O
scale	O
out	O
applications	O
,	O
and	O
two	O
12	O
core	O
SMT8	O
versions	O
intended	O
to	O
use	O
PowerVM	O
for	O
scale-up	O
and	O
scale-out	O
applications	O
.	O
</s>
<s>
Possibly	O
there	O
will	O
be	O
more	O
versions	O
in	O
the	O
future	O
since	O
the	O
POWER9	B-Device
architecture	O
is	O
open	O
for	O
licensing	O
and	O
modification	O
by	O
the	O
OpenPOWER	B-Application
Foundation	I-Application
members	O
.	O
</s>
<s>
Power10	B-Operating_System
is	O
a	O
CPU	O
introduced	O
in	O
September	O
2021	O
.	O
</s>
<s>
Name	O
Image	O
ISA	O
Bits	O
Cores	O
Fab	O
Transistors	O
Die	O
size	O
L1	O
L2	O
L3	O
Clock	O
Package	O
Introduced	O
RIOS-1	B-General_Concept
POWER	B-Architecture
32	O
bits	O
1	O
1.0	O
μm	O
6.9	O
M	O
1284	O
mm2	O
8	O
KB	O
I64	O
KB	O
D	O
n/a	O
n/a	O
20	O
–	O
30	O
MHz	O
10	O
chipsin	O
CPGAon	O
PCB	O
1990	O
RIOS.9	O
100px	O
POWER	B-Architecture
32	O
bits	O
1	O
1.0	O
μm	O
6.9	O
M	O
8	O
KB	O
I32	O
KB	O
D	O
n/a	O
n/a	O
20	O
–	O
30	O
MHz	O
8	O
chipsin	O
CPGAon	O
PCB	O
1990	O
POWER1+	B-General_Concept
POWER	B-Architecture
32	O
bits	O
1	O
6.9	O
M	O
8	O
KB	O
I64	O
KB	O
D	O
n/a	O
n/a	O
25	O
–	O
41.6	O
MHz	O
8	O
chipsin	O
CPGAon	O
PCB	O
1991	O
POWER1++	O
POWER	B-Architecture
32	O
bits	O
1	O
6.9	O
M	O
8	O
KB	O
I64	O
KB	O
D	O
n/a	O
n/a	O
25	O
–	O
62.5	O
MHz	O
8	O
chipsin	O
CPGAon	O
PCB	O
1992	O
RSC	B-Device
100px	O
POWER	B-Architecture
32	O
bits	O
1	O
0.8	O
μm	O
1	O
M	O
226.5	O
mm2	O
8	O
KBunified	O
n/a	O
n/a	O
33	O
–	O
45	O
MHz	O
201	O
pin	O
CPGA	O
1992	O
POWER2	B-General_Concept
100px	O
POWER2	B-General_Concept
32	O
bits	O
1	O
0.72	O
μm	O
23	O
M	O
1042.5	O
mm2819	O
mm2	O
32	O
KB	O
I128	O
–	O
265	O
KB	O
D	O
n/a	O
n/a	O
55	O
–	O
71.5	O
MHz	O
6	O
–	O
8	O
dieson	O
ceramic	B-Algorithm
734	O
pin	O
MCM	O
1993	O
POWER2+	B-General_Concept
100px	O
POWER2	B-General_Concept
32	O
bits	O
1	O
0.72	O
μm	O
23	O
M	O
819	O
mm2	O
32	O
KB	O
I64	O
–	O
128	O
KB	O
D	O
0.5	O
–	O
2	O
MBexternal	O
n/a	O
55	O
–	O
71.5	O
MHz	O
6	O
chipsin	O
CBGAon	O
PCB	O
1994	O
P2SC	O
POWER2	B-General_Concept
32	O
bits	O
1	O
0.29	O
μm	O
15	O
M	O
335	O
mm2	O
32	O
KB	O
I128	O
KB	O
D	O
n/a	O
n/a	O
120	O
–	O
135	O
MHz	O
CCGA	O
1996	O
P2SC+	O
100px	O
POWER2	B-General_Concept
32	O
bits	O
1	O
0.25	O
μm	O
15	O
M	O
256	O
mm2	O
32	O
KB	O
I128	O
KB	O
D	O
n/a	O
n/a	O
160	O
MHz	O
CCGA	O
1997	O
RAD6000	B-Device
100px	O
POWER	B-Architecture
32	O
bits	O
1	O
0.5	O
μm	O
1.1	O
M	O
8	O
KB	O
unified	O
n/a	O
n/a	O
20	O
–	O
33	O
MHz	O
Rad	O
hard	O
1997	O
POWER3	B-General_Concept
100px	O
POWER2PowerPC	O
1.1	O
64	O
bits	O
1	O
0.35	O
μm	O
15	O
M	O
270	O
mm2	O
32	O
KB	O
I64	O
KB	O
D	O
1	O
–	O
16	O
MBexternal	O
n/a	O
200	O
–	O
222	O
MHz	O
1088	O
pin	O
CLGA	O
1998	O
POWER3-II	O
100px	O
POWER2PowerPC	O
1.1	O
64	O
bits	O
1	O
0.25	O
μm	O
Cu	O
23	O
M	O
170	O
mm2	O
32	O
KB	O
I64	O
KB	O
D	O
1	O
–	O
16	O
MBexternal	O
n/a	O
333	O
–	O
450	O
MHz	O
1088	O
pin	O
CLGA	O
1999	O
POWER4	B-Device
100px	O
PowerPC	B-Architecture
2.00PowerPC-AS	O
64	O
bits	O
2	O
180	O
nm	O
174	O
M	O
412	O
mm2	O
64	O
KB	O
I32	O
KB	O
Dper	O
core	O
1.41	O
MBper	O
core	O
32	O
MBexternal	O
1	O
–	O
1.3	O
GHz	O
1024	O
pin	O
CLGAceramic	O
MCM	O
2001	O
POWER4+	B-Device
100px	O
PowerPC	B-Architecture
2.01PowerPC-AS	O
64	O
bits	O
2	O
130	O
nm	O
184	O
M	O
267	O
mm2	O
64	O
KB	O
I32	O
KB	O
Dper	O
core	O
1.41	O
MBper	O
chip	O
32	O
MBexternal	O
1.2	O
–	O
1.9	O
GHz	O
1024	O
pin	O
CLGAceramic	O
MCM	O
2002	O
POWER5	B-Device
100px	O
PowerPC	B-Architecture
2.02Power	O
ISA	O
2.03	O
64	O
bits	O
2	O
130	O
nm	O
276	O
M	O
389	O
mm2	O
32	O
KB	O
I32	O
KB	O
Dper	O
core	O
1.875	O
MBper	O
chip	O
32	O
MBexternal	O
1.5	O
–	O
1.9	O
GHz	O
ceramic	B-Algorithm
DCMceramic	O
MCM	O
2004	O
POWER5+	O
100px	O
PowerPC	B-Architecture
2.02Power	O
ISA	O
2.03	O
64	O
bits	O
2	O
90	O
nm	O
276	O
M	O
243	O
mm2	O
32	O
KB	O
I32	O
KB	O
Dper	O
core	O
1.875	O
MBper	O
chip	O
32	O
MBexternal	O
1.5	O
–	O
2.3	O
GHz	O
ceramic	B-Algorithm
DCMceramic	O
QCMceramic	O
MCM	O
2005	O
POWER6	B-Device
100px	O
Power	B-Architecture
ISA	I-Architecture
2.03	O
64	O
bits	O
2	O
65	O
nm	O
790	O
M	O
341	O
mm2	O
64	O
KB	O
I64	O
KB	O
Dper	O
core	O
4	O
MBper	O
core	O
32	O
MBexternal	O
3.6	O
–	O
5	O
GHz	O
CLGAOLGA	O
2007	O
POWER6+	O
100px	O
Power	B-Architecture
ISA	I-Architecture
2.03	O
64	O
bits	O
2	O
65	O
nm	O
790	O
M	O
341	O
mm2	O
64	O
KB	O
I64	O
KB	O
Dper	O
core	O
4	O
MBper	O
core	O
32	O
MBexternal	O
3.6	O
–	O
5	O
GHz	O
CLGAOLGA	O
2009	O
POWER7	B-Device
100px	O
Power	B-Architecture
ISA	I-Architecture
2.06	O
64	O
bits	O
8	O
45	O
nm	O
1.2	O
B	O
567	O
mm2	O
32	O
KB	O
I32	O
KB	O
Dper	O
core	O
256	O
KBper	O
core	O
32	O
MBper	O
chip	O
2.4	O
–	O
4.25	O
GHz	O
CLGAOLGAorganic	O
QCM	O
2010	O
POWER7+	O
100px	O
Power	B-Architecture
ISA	I-Architecture
2.06	O
64	O
bits	O
8	O
32	O
nm	O
2.1	O
B	O
567	O
mm2	O
32	O
KB	O
I32	O
KB	O
Dper	O
core	O
256	O
KBper	O
core	O
80	O
MBper	O
chip	O
2.4	O
–	O
4.4	O
GHz	O
OLGAorganic	O
DCM	O
2012	O
POWER8	B-Device
100px	O
Power	B-Architecture
ISA	I-Architecture
2.07	O
64	O
bits	O
612	O
22	O
nm	O
?	O
</s>
