<s>
IBM	O
POWER	B-Architecture
is	O
a	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
developed	O
by	O
IBM	O
.	O
</s>
<s>
The	O
name	O
is	O
an	O
acronym	O
for	O
Performance	O
Optimization	O
With	O
Enhanced	O
RISC	B-Architecture
.	O
</s>
<s>
The	O
ISA	O
is	O
used	O
as	O
base	O
for	O
high	O
end	O
microprocessors	O
from	O
IBM	O
during	O
the	O
1990s	O
and	O
were	O
used	O
in	O
many	O
of	O
IBM	O
's	O
servers	O
,	O
minicomputers	O
,	O
workstations	B-Device
,	O
and	O
supercomputers	O
.	O
</s>
<s>
These	O
processors	O
are	O
called	O
POWER1	B-General_Concept
(	O
RIOS-1	O
,	O
RIOS.9	O
,	O
RSC	B-Device
,	O
RAD6000	B-Device
)	O
and	O
POWER2	B-General_Concept
(	O
POWER2	B-General_Concept
,	O
POWER2+	B-General_Concept
and	O
P2SC	O
)	O
.	O
</s>
<s>
The	O
ISA	O
evolved	O
into	O
the	O
PowerPC	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
and	O
was	O
deprecated	O
in	O
1998	O
when	O
IBM	O
introduced	O
the	O
POWER3	B-General_Concept
processor	O
that	O
was	O
mainly	O
a	O
32/64	O
-bit	O
PowerPC	B-Architecture
processor	I-Architecture
but	O
included	O
the	O
IBM	B-Architecture
POWER	I-Architecture
architecture	I-Architecture
for	O
backwards	O
compatibility	O
.	O
</s>
<s>
The	O
original	O
IBM	B-Architecture
POWER	I-Architecture
architecture	I-Architecture
was	O
then	O
abandoned	O
.	O
</s>
<s>
PowerPC	B-Architecture
evolved	O
into	O
the	O
third	O
Power	B-Architecture
ISA	I-Architecture
in	O
2006	O
.	O
</s>
<s>
IBM	O
continues	O
to	O
develop	O
PowerPC	B-Architecture
microprocessor	O
cores	O
for	O
use	O
in	O
their	O
application-specific	O
integrated	O
circuit	O
(	O
ASIC	O
)	O
offerings	O
.	O
</s>
<s>
Many	O
high	O
volume	O
applications	O
embed	O
PowerPC	B-Architecture
cores	O
.	O
</s>
<s>
This	O
requirement	O
was	O
extremely	O
ambitious	O
for	O
the	O
time	O
,	O
but	O
it	O
was	O
realised	O
that	O
much	O
of	O
the	O
complexity	O
of	O
contemporary	O
CPUs	O
could	O
be	O
dispensed	O
with	O
,	O
since	O
this	O
machine	O
would	O
need	O
only	O
to	O
perform	O
I/O	O
,	O
branches	O
,	O
add	O
register-register	O
,	O
move	O
data	O
between	O
registers	O
and	O
memory	O
,	O
and	O
would	O
have	O
no	O
need	O
for	O
special	O
instructions	O
to	O
perform	O
heavy	O
arithmetic	O
.	O
</s>
<s>
This	O
simple	O
design	O
philosophy	O
,	O
whereby	O
each	O
step	O
of	O
a	O
complex	O
operation	O
is	O
specified	O
explicitly	O
by	O
one	O
machine	O
instruction	O
,	O
and	O
all	O
instructions	O
are	O
required	O
to	O
complete	O
in	O
the	O
same	O
constant	O
time	O
,	O
would	O
later	O
come	O
to	O
be	O
known	O
as	O
RISC	B-Architecture
.	O
</s>
<s>
From	O
the	O
estimates	O
from	O
simulations	O
produced	O
in	O
the	O
project	O
's	O
first	O
year	O
,	O
however	O
,	O
it	O
looked	O
as	O
if	O
the	O
processor	O
being	O
designed	O
for	O
this	O
project	O
could	O
be	O
a	O
very	O
promising	O
general-purpose	O
processor	O
,	O
so	O
work	O
continued	O
at	O
Thomas	O
J	O
.	O
Watson	O
Research	O
Center	O
building	O
#801	O
,	O
on	O
the	O
801	B-Device
project	O
.	O
</s>
<s>
For	O
two	O
years	O
at	O
the	O
Watson	O
Research	O
Center	O
,	O
the	O
superscalar	B-General_Concept
limits	O
of	O
the	O
801	B-Device
design	O
were	O
explored	O
,	O
such	O
as	O
the	O
feasibility	O
of	O
implementing	O
the	O
design	O
using	O
multiple	O
functional	B-General_Concept
units	I-General_Concept
to	O
improve	O
performance	O
,	O
similar	O
to	O
what	O
had	O
been	O
done	O
in	O
the	O
IBM	B-Device
System/360	I-Device
Model	I-Device
91	I-Device
and	O
the	O
CDC	B-Device
6600	I-Device
(	O
although	O
the	O
Model	O
91	O
had	O
been	O
based	O
on	O
a	O
CISC	O
design	O
)	O
,	O
to	O
determine	O
if	O
a	O
RISC	B-Architecture
machine	O
could	O
maintain	O
multiple	O
instructions	O
per	O
cycle	O
,	O
or	O
what	O
design	O
changes	O
need	O
to	O
be	O
made	O
to	O
the	O
801	B-Device
design	O
to	O
allow	O
for	O
multiple-execution-units	O
.	O
</s>
<s>
To	O
increase	O
performance	O
,	O
Cheetah	O
had	O
separate	O
branch	O
,	O
fixed-point	O
,	O
and	O
floating-point	B-Algorithm
execution	B-General_Concept
units	I-General_Concept
.	O
</s>
<s>
Many	O
changes	O
were	O
made	O
to	O
the	O
801	B-Device
design	O
to	O
allow	O
for	O
multiple-execution-units	O
.	O
</s>
<s>
Cheetah	O
was	O
originally	O
planned	O
to	O
be	O
manufactured	O
using	O
bipolar	O
emitter-coupled	B-General_Concept
logic	I-General_Concept
(	O
ECL	O
)	O
technology	O
,	O
but	O
by	O
1984	O
complementary	O
metal	O
–	O
oxide	O
–	O
semiconductor	O
(	O
CMOS	B-Device
)	O
technology	O
afforded	O
an	O
increase	O
in	O
the	O
level	O
of	O
circuit	O
integration	O
while	O
improving	O
transistor-logic	O
performance	O
.	O
</s>
<s>
In	O
1985	O
,	O
research	O
on	O
a	O
second-generation	O
RISC	B-Architecture
architecture	O
started	O
at	O
the	O
IBM	O
Thomas	O
J	O
.	O
Watson	O
Research	O
Center	O
,	O
producing	O
the	O
"	O
AMERICA	O
architecture	O
"	O
;	O
in	O
1986	O
,	O
IBM	O
Austin	O
started	O
developing	O
the	O
RS/6000	B-Device
series	O
,	O
based	O
on	O
that	O
architecture	O
.	O
</s>
<s>
In	O
February	O
1990	O
,	O
the	O
first	O
computers	O
from	O
IBM	O
to	O
incorporate	O
the	O
POWER	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
were	O
called	O
the	O
"	O
RISC	B-Device
System/6000	I-Device
"	O
or	O
RS/6000	B-Device
.	O
</s>
<s>
These	O
RS/6000	B-Device
computers	O
were	O
divided	O
into	O
two	O
classes	O
,	O
workstations	B-Device
and	O
servers	O
,	O
and	O
hence	O
introduced	O
as	O
the	O
POWERstation	O
and	O
POWERserver	O
.	O
</s>
<s>
The	O
RS/6000	B-Device
CPU	O
had	O
2	O
configurations	O
,	O
called	O
the	O
"	O
RIOS-1	O
"	O
and	O
"	O
RIOS.9	O
"	O
(	O
or	O
more	O
commonly	O
the	O
"	O
POWER1	B-General_Concept
"	O
CPU	O
)	O
.	O
</s>
<s>
A	O
RIOS-1	O
configuration	O
had	O
a	O
total	O
of	O
10	O
discrete	O
chips	O
-	O
an	O
instruction	O
cache	O
chip	O
,	O
fixed-point	O
chip	O
,	O
floating-point	B-Algorithm
chip	O
,	O
4	O
data	O
cache	O
chips	O
,	O
storage	O
control	O
chip	O
,	O
input/output	O
chips	O
,	O
and	O
a	O
clock	O
chip	O
.	O
</s>
<s>
The	O
lower	O
cost	O
RIOS.9	O
configuration	O
had	O
8	O
discrete	O
chips	O
-	O
an	O
instruction	O
cache	O
chip	O
,	O
fixed-point	O
chip	O
,	O
floating-point	B-Algorithm
chip	O
,	O
2	O
data	O
cache	O
chips	O
,	O
storage	O
control	O
chip	O
,	O
input/output	O
chip	O
,	O
and	O
a	O
clock	O
chip	O
.	O
</s>
<s>
A	O
single-chip	O
implementation	O
of	O
RIOS	O
,	O
RSC	B-Device
(	O
for	O
"	O
RISC	B-Device
Single	I-Device
Chip	I-Device
"	O
)	O
,	O
was	O
developed	O
for	O
lower-end	O
RS/6000	B-Device
'	O
s	O
;	O
the	O
first	O
machines	O
using	O
RSC	B-Device
were	O
released	O
in	O
1992	O
.	O
</s>
<s>
IBM	O
started	O
the	O
POWER2	B-General_Concept
processor	O
effort	O
as	O
a	O
successor	O
to	O
the	O
POWER1	B-General_Concept
two	O
years	O
before	O
the	O
creation	O
of	O
the	O
1991	O
Apple/IBM/Motorola	O
alliance	O
in	O
Austin	O
,	O
Texas	O
.	O
</s>
<s>
Despite	O
being	O
impacted	O
by	O
diversion	O
of	O
resources	O
to	O
jump	O
start	O
the	O
Apple/IBM/Motorola	O
effort	O
,	O
the	O
POWER2	B-General_Concept
took	O
five	O
years	O
from	O
start	O
to	O
system	O
shipment	O
.	O
</s>
<s>
By	O
adding	O
a	O
second	O
fixed-point	O
unit	O
,	O
a	O
second	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
,	O
and	O
other	O
performance	O
enhancements	O
to	O
the	O
design	O
,	O
the	O
POWER2	B-General_Concept
had	O
leadership	O
performance	O
when	O
it	O
was	O
announced	O
in	O
November	O
1993	O
.	O
</s>
<s>
New	O
instructions	O
were	O
also	O
added	O
to	O
the	O
instruction	B-General_Concept
set	I-General_Concept
:	O
</s>
<s>
The	O
quad-word	O
load	O
instruction	O
moves	O
two	O
adjacent	O
double-precision	O
values	O
into	O
two	O
adjacent	O
floating-point	B-Algorithm
registers	O
.	O
</s>
<s>
Floating-point	B-Algorithm
to	O
integer	O
conversion	O
instructions	O
.	O
</s>
<s>
To	O
support	O
the	O
RS/6000	B-Device
and	O
RS/6000	B-Device
SP2	O
product	O
lines	O
in	O
1996	O
,	O
IBM	O
had	O
its	O
own	O
design	O
team	O
implement	O
a	O
single-chip	O
version	O
of	O
POWER2	B-General_Concept
,	O
the	O
P2SC	O
(	O
"	O
POWER2	B-General_Concept
Super	O
Chip	O
"	O
)	O
,	O
outside	O
the	O
Apple/IBM/Motorola	O
alliance	O
in	O
IBM	O
's	O
most	O
advanced	O
and	O
dense	O
CMOS-6S	O
process	O
.	O
</s>
<s>
P2SC	O
combined	O
all	O
of	O
the	O
separate	O
POWER2	B-General_Concept
instruction	O
cache	O
,	O
fixed	O
point	O
,	O
floating	B-Algorithm
point	I-Algorithm
,	O
storage	O
control	O
,	O
and	O
data	O
cache	O
chips	O
onto	O
one	O
huge	O
die	O
.	O
</s>
<s>
Despite	O
the	O
challenge	O
of	O
its	O
size	O
,	O
complexity	O
,	O
and	O
advanced	O
CMOS	B-Device
process	O
,	O
the	O
first	O
tape-out	O
version	O
of	O
the	O
processor	O
was	O
able	O
to	O
be	O
shipped	O
,	O
and	O
it	O
had	O
leadership	O
floating	B-Algorithm
point	I-Algorithm
performance	O
at	O
the	O
time	O
it	O
was	O
announced	O
.	O
</s>
<s>
P2SC	O
was	O
the	O
processor	O
used	O
in	O
the	O
1997	O
IBM	B-General_Concept
Deep	I-General_Concept
Blue	I-General_Concept
chess	O
playing	O
supercomputer	O
which	O
beat	O
chess	O
grandmaster	O
Garry	O
Kasparov	O
.	O
</s>
<s>
With	O
its	O
twin	O
sophisticated	O
MAF	O
floating	B-General_Concept
point	I-General_Concept
units	I-General_Concept
and	O
huge	O
wide	O
and	O
low	O
latency	O
memory	O
interfaces	O
,	O
P2SC	O
was	O
primarily	O
targeted	O
at	O
engineering	O
and	O
scientific	O
applications	O
.	O
</s>
<s>
P2SC	O
was	O
eventually	O
succeeded	O
by	O
the	O
POWER3	B-General_Concept
,	O
which	O
included	O
64-bit	O
,	O
SMP	O
capability	O
,	O
and	O
a	O
full	O
transition	O
to	O
PowerPC	B-Architecture
in	O
addition	O
to	O
P2SC	O
's	O
sophisticated	O
twin	O
MAF	O
floating	B-General_Concept
point	I-General_Concept
units	I-General_Concept
.	O
</s>
<s>
The	O
POWER	B-Architecture
design	O
is	O
descended	O
directly	O
from	O
the	O
801	B-Device
's	O
CPU	O
,	O
widely	O
considered	O
to	O
be	O
the	O
first	O
true	O
RISC	B-Architecture
processor	I-Architecture
design	O
.	O
</s>
<s>
The	O
801	B-Device
was	O
used	O
in	O
a	O
number	O
of	O
applications	O
inside	O
IBM	O
hardware	O
.	O
</s>
<s>
They	O
were	O
interested	O
primarily	O
in	O
fixing	O
two	O
problems	O
in	O
the	O
801	B-Device
design	O
:	O
</s>
<s>
The	O
801	B-Device
required	O
all	O
instructions	O
to	O
complete	O
in	O
one	O
clock	O
cycle	O
,	O
which	O
precluded	O
floating	B-Algorithm
point	I-Algorithm
instructions	O
.	O
</s>
<s>
Although	O
the	O
decoder	O
was	O
pipelined	O
as	O
a	O
side	O
effect	O
of	O
these	O
single-cycle	O
operations	O
,	O
they	O
did	O
n't	O
use	O
superscalar	B-General_Concept
effects	O
.	O
</s>
<s>
Floating	B-Algorithm
point	I-Algorithm
became	O
a	O
focus	O
for	O
the	O
America	O
Project	O
,	O
and	O
IBM	O
was	O
able	O
to	O
use	O
new	O
algorithms	O
developed	O
in	O
the	O
early	O
1980s	O
that	O
could	O
support	O
64-bit	O
double-precision	O
multiplies	O
and	O
divides	O
in	O
a	O
single	O
cycle	O
.	O
</s>
<s>
The	O
FPU	B-General_Concept
portion	O
of	O
the	O
design	O
was	O
separate	O
from	O
the	O
instruction	O
decoder	O
and	O
integer	O
parts	O
,	O
allowing	O
the	O
decoder	O
to	O
send	O
instructions	O
to	O
both	O
the	O
FPU	B-General_Concept
and	O
ALU	B-General_Concept
(	O
integer	O
)	O
execution	B-General_Concept
units	I-General_Concept
at	O
the	O
same	O
time	O
.	O
</s>
<s>
IBM	O
complemented	O
this	O
with	O
a	O
complex	O
instruction	O
decoder	O
which	O
could	O
be	O
fetching	O
one	O
instruction	O
,	O
decoding	O
another	O
,	O
and	O
sending	O
one	O
to	O
the	O
ALU	B-General_Concept
and	O
FPU	B-General_Concept
at	O
the	O
same	O
time	O
,	O
resulting	O
in	O
one	O
of	O
the	O
first	O
superscalar	B-General_Concept
CPU	O
designs	O
in	O
use	O
.	O
</s>
<s>
The	O
system	O
used	O
32	O
32-bit	O
integer	O
registers	O
and	O
another	O
32	O
64-bit	O
floating	B-Algorithm
point	I-Algorithm
registers	O
,	O
each	O
in	O
their	O
own	O
unit	O
.	O
</s>
<s>
The	O
branch	O
unit	O
also	O
included	O
a	O
number	O
of	O
"	O
private	O
"	O
registers	O
for	O
its	O
own	O
use	O
,	O
including	O
the	O
program	B-General_Concept
counter	I-General_Concept
.	O
</s>
<s>
Appendix	O
E	O
of	O
Book	O
I	O
:	O
PowerPC	B-Architecture
User	O
Instruction	B-General_Concept
Set	I-General_Concept
Architecture	I-General_Concept
of	O
the	O
PowerPC	B-Architecture
Architecture	O
Book	O
,	O
Version	O
2.02	O
describes	O
the	O
differences	O
between	O
the	O
POWER	B-Architecture
and	O
POWER2	B-General_Concept
instruction	B-General_Concept
set	I-General_Concept
architectures	I-General_Concept
and	O
the	O
version	O
of	O
the	O
PowerPC	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
implemented	O
by	O
the	O
POWER5	O
.	O
</s>
