<s>
The	O
IBM	B-Device
A2	I-Device
is	O
an	O
open	B-License
source	I-License
massively	O
multicore	B-Architecture
capable	O
and	O
multithreaded	B-General_Concept
64-bit	B-Device
Power	B-Architecture
ISA	I-Architecture
processor	O
core	O
designed	O
by	O
IBM	O
using	O
the	O
Power	B-Architecture
ISA	I-Architecture
v.2.06	O
specification	O
.	O
</s>
<s>
The	O
A2	O
core	O
is	O
a	O
processor	O
core	O
designed	O
for	O
customization	O
and	O
embedded	O
use	O
in	O
system	O
on	O
chip-devices	O
,	O
and	O
was	O
developed	O
following	O
IBM	O
's	O
game	B-Device
console	I-Device
processor	O
designs	O
,	O
the	O
Xbox	B-Device
360-processor	I-Device
and	O
Cell	B-General_Concept
processor	I-General_Concept
for	O
the	O
PlayStation	B-Operating_System
3	I-Operating_System
.	O
</s>
<s>
A2I	O
is	O
a	O
4-way	O
simultaneous	O
multithreaded	B-General_Concept
core	O
which	O
implements	O
the	O
64-bit	B-Device
Power	B-Architecture
ISA	I-Architecture
v.2.06	O
Book	O
III-E	O
embedded	O
platform	O
specification	O
with	O
support	O
for	O
the	O
embedded	B-Application
hypervisor	I-Application
features	O
.	O
</s>
<s>
A2I	O
was	O
written	O
in	O
VHDL	B-Language
.	O
</s>
<s>
The	O
core	O
has	O
4×32	O
64-bit	B-Device
general	O
purpose	O
registers	O
(	O
GPR	O
)	O
with	O
full	O
support	O
for	O
both	O
little	O
and	O
big	O
endian	O
byte	O
ordering	O
,	O
16KB+16KB	O
instruction	O
and	O
data	B-General_Concept
cache	I-General_Concept
and	O
is	O
capable	O
of	O
four-way	O
multithreading	B-General_Concept
.	O
</s>
<s>
It	O
has	O
a	O
fine	O
grain	O
branch	B-General_Concept
prediction	I-General_Concept
unit	I-General_Concept
(	O
BPU	O
)	O
with	O
eight	O
1024-entry	O
branch	O
history	O
tables	O
.	O
</s>
<s>
The	O
L1	O
caches	O
is	O
a	O
16KB	O
8-way	O
set-associative	O
data	B-General_Concept
cache	I-General_Concept
and	O
a	O
4-way	O
set-associative	O
16KB	O
instruction	O
cache	B-General_Concept
.	O
</s>
<s>
It	O
includes	O
a	O
memory	O
management	O
unit	O
but	O
no	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
.	O
</s>
<s>
Such	O
facilities	O
are	O
handled	O
by	O
the	O
AXU	O
,	O
which	O
has	O
support	O
for	O
any	O
number	O
of	O
standardized	O
or	O
customized	O
macros	O
,	O
such	O
as	O
floating	B-General_Concept
point	I-General_Concept
units	I-General_Concept
,	O
vector	O
units	O
,	O
DSPs	O
,	O
media	O
accelerators	O
and	O
other	O
units	O
with	O
instruction	O
sets	O
and	O
registers	O
not	O
part	O
of	O
the	O
Power	B-Architecture
ISA	I-Architecture
.	O
</s>
<s>
The	O
A2O	O
is	O
a	O
slightly	O
more	O
modern	O
version	O
,	O
written	O
in	O
Verilog	B-Language
,	O
using	O
the	O
Power	B-Architecture
ISA	I-Architecture
v.2.07	O
Book	O
III-E	O
.	O
</s>
<s>
It	O
is	O
optimized	O
for	O
single	O
core	O
performance	O
and	O
designed	O
to	O
reach	O
3	O
GHz	O
at	O
45	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
technology	O
.	O
</s>
<s>
The	O
A2O	O
differs	O
from	O
its	O
sibling	O
in	O
that	O
it	O
is	O
only	O
two-way	O
multithreaded	B-General_Concept
,	O
32+32	O
kB	O
data	O
and	O
instruction	O
L1	O
caches	O
,	O
and	O
is	O
capable	O
of	O
out-of-order	O
execution	O
.	O
</s>
<s>
In	O
the	O
second	O
half	O
of	O
2020	O
IBM	O
released	O
the	O
A2I	O
and	O
A2O	O
cores	O
under	O
a	O
Creative	O
Commons	O
license	O
,	O
and	O
published	O
the	O
VHDL	B-Language
and	O
Verilog	B-Language
code	O
on	O
GitHub	B-Application
.	O
</s>
<s>
The	O
intention	O
was	O
to	O
add	O
them	O
to	O
the	O
OpenPOWER	B-Application
Foundation	I-Application
's	O
offerings	O
of	O
free	O
and	O
open	O
processor	O
cores	O
.	O
</s>
<s>
As	O
A2	O
was	O
designed	O
in	O
2010	O
,	O
A2I	O
and	O
A2O	O
are	O
not	O
compliant	O
with	O
the	O
Power	B-Architecture
ISA	I-Architecture
3.0	O
or	O
3.1	O
which	O
is	O
mandatory	O
for	O
OpenPOWER	B-Application
cores	O
.	O
</s>
<s>
The	O
PowerEN	B-Device
(	O
Power	B-Device
Edge	I-Device
of	I-Device
Network	I-Device
)	O
,	O
or	O
the	O
"	O
wire-speed	O
processor	O
"	O
,	O
is	O
designed	O
as	O
hybrid	O
between	O
regular	O
networking	B-General_Concept
processors	I-General_Concept
,	O
doing	O
switching	B-Protocol
and	O
routing	B-Protocol
and	O
a	O
typical	O
server	O
processor	O
,	O
that	O
is	O
manipulating	O
and	O
packaging	O
data	O
.	O
</s>
<s>
Each	O
chip	O
uses	O
the	O
A2I	O
core	O
and	O
has	O
8MB	O
of	O
cache	B-General_Concept
as	O
well	O
a	O
multitude	O
of	O
task-specific	O
engines	O
besides	O
the	O
general-purpose	O
processors	O
,	O
such	O
as	O
XML	B-Protocol
,	O
cryptography	O
,	O
compression	B-General_Concept
and	O
regular	B-Language
expression	I-Language
accelerators	O
each	O
with	O
MMUs	O
of	O
their	O
own	O
,	O
four	O
10	O
Gigabit	O
Ethernet	O
ports	O
and	O
two	O
PCIe	O
lanes	O
.	O
</s>
<s>
Up	O
to	O
four	O
chips	O
can	O
be	O
linked	O
in	O
a	O
SMP	B-Operating_System
system	O
without	O
any	O
additional	O
support	O
chips	O
.	O
</s>
<s>
The	O
chips	O
are	O
said	O
to	O
be	O
extremely	O
complex	O
according	O
to	O
Charlie	O
Johnson	O
,	O
chief	O
architect	O
at	O
IBM	O
,	O
and	O
use	O
1.43	O
billion	O
transistors	O
on	O
a	O
die	O
size	O
of	O
428mm²	O
fabricated	B-Architecture
using	O
a	O
45	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
.	O
</s>
<s>
The	O
Blue	B-Operating_System
Gene/Q	I-Operating_System
processor	O
is	O
an	O
18	O
core	O
chip	O
using	O
the	O
A2I	O
core	O
running	O
at	O
1.6GHz	O
with	O
special	O
features	O
for	O
fast	O
thread	O
context	O
switching	B-Protocol
,	O
quad	O
SIMD	B-Device
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
,	O
5D	O
torus	O
chip-to-chip	O
network	O
and	O
2	O
GB/s	O
external	O
I/O	O
.	O
</s>
<s>
The	O
cores	O
are	O
linked	O
by	O
a	O
crossbar	O
switch	O
at	O
half	O
core	O
speed	O
to	O
a	O
32MB	O
eDRAM	O
L2	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
L2	B-General_Concept
cache	I-General_Concept
is	O
multi-versioned	O
and	O
supports	O
transactional	B-Operating_System
memory	I-Operating_System
and	O
speculative	B-Operating_System
execution	I-Operating_System
.	O
</s>
<s>
A	O
Blue	B-Operating_System
Gene/Q	I-Operating_System
chip	O
has	O
two	O
DDR3	O
memory	O
controllers	O
running	O
at	O
1.33GHz	O
,	O
supporting	O
up	O
to	O
16	O
GB	O
RAM	O
.	O
</s>
<s>
This	O
17th	O
core	O
will	O
take	O
care	O
of	O
interrupts	B-Application
,	O
asynchronous	B-Architecture
I/O	I-Architecture
,	O
MPI	O
flow	O
control	O
,	O
and	O
RAS	B-General_Concept
functionality	O
.	O
</s>
<s>
The	O
Blue	B-Operating_System
Gene/Q	I-Operating_System
chip	O
is	O
manufactured	O
on	O
IBM	O
's	O
copper	O
SOI	O
process	O
at	O
45nm	B-Algorithm
,	O
will	O
deliver	O
a	O
peak	O
performance	O
of	O
204.8	O
GFLOPS	O
at	O
1.6GHz	O
and	O
draws	O
about	O
55	O
watts	O
.	O
</s>
