<s>
IA-64	B-General_Concept
(	O
Intel	B-General_Concept
Itanium	I-General_Concept
architecture	I-General_Concept
)	O
is	O
the	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
of	O
the	O
Itanium	B-General_Concept
family	O
of	O
64-bit	B-Device
Intel	O
microprocessors	B-Architecture
.	O
</s>
<s>
The	O
first	O
Itanium	B-General_Concept
processor	O
,	O
codenamed	B-Architecture
Merced	O
,	O
was	O
released	O
in	O
2001	O
.	O
</s>
<s>
The	O
Itanium	B-General_Concept
architecture	O
is	O
based	O
on	O
explicit	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
,	O
in	O
which	O
the	O
compiler	B-Language
decides	O
which	O
instructions	O
to	O
execute	O
in	O
parallel	O
.	O
</s>
<s>
This	O
contrasts	O
with	O
superscalar	B-General_Concept
architectures	I-General_Concept
,	O
which	O
depend	O
on	O
the	O
processor	O
to	O
manage	O
instruction	O
dependencies	O
at	O
runtime	O
.	O
</s>
<s>
In	O
all	O
Itanium	B-General_Concept
models	O
,	O
up	O
to	O
and	O
including	O
Tukwila	B-General_Concept
,	O
cores	O
execute	O
up	O
to	O
six	O
instructions	O
per	O
clock	O
cycle	O
.	O
</s>
<s>
In	O
2008	O
,	O
Itanium	B-General_Concept
was	O
the	O
fourth-most	O
deployed	O
microprocessor	B-Architecture
architecture	O
for	O
enterprise-class	B-General_Concept
systems	I-General_Concept
,	O
behind	O
x86-64	B-Device
,	O
Power	B-Architecture
ISA	I-Architecture
,	O
and	O
SPARC	B-Architecture
.	O
</s>
<s>
In	O
1989	O
,	O
HP	O
began	O
to	O
become	O
concerned	O
that	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computing	I-Architecture
(	O
RISC	B-Architecture
)	O
architectures	O
were	O
approaching	O
a	O
processing	O
limit	O
at	O
one	O
instruction	O
per	O
cycle	O
.	O
</s>
<s>
Both	O
Intel	O
and	O
HP	O
researchers	O
had	O
been	O
exploring	O
computer	O
architecture	O
options	O
for	O
future	O
designs	O
and	O
separately	O
began	O
investigating	O
a	O
new	O
concept	O
known	O
as	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
which	O
came	O
out	O
of	O
research	O
by	O
Yale	O
University	O
in	O
the	O
early	O
1980s	O
.	O
</s>
<s>
VLIW	B-General_Concept
is	O
a	O
computer	O
architecture	O
concept	O
(	O
like	O
RISC	B-Architecture
and	O
CISC	B-Architecture
)	O
where	O
a	O
single	O
instruction	O
word	O
contains	O
multiple	O
instructions	O
encoded	O
in	O
one	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
to	O
facilitate	O
the	O
processor	O
executing	O
multiple	O
instructions	O
in	O
each	O
clock	O
cycle	O
.	O
</s>
<s>
Typical	O
VLIW	B-General_Concept
implementations	O
rely	O
heavily	O
on	O
sophisticated	O
compilers	B-Language
to	O
determine	O
at	O
compile	B-Language
time	O
which	O
instructions	O
can	O
be	O
executed	O
at	O
the	O
same	O
time	O
and	O
the	O
proper	O
scheduling	O
of	O
these	O
instructions	O
for	O
execution	O
and	O
also	O
to	O
help	O
predict	O
the	O
direction	O
of	O
branch	O
operations	O
.	O
</s>
<s>
The	O
value	O
of	O
this	O
approach	O
is	O
to	O
do	O
more	O
useful	O
work	O
in	O
fewer	O
clock	O
cycles	O
and	O
to	O
simplify	O
processor	O
instruction	O
scheduling	O
and	O
branch	B-General_Concept
prediction	I-General_Concept
hardware	O
requirements	O
,	O
with	O
a	O
penalty	O
in	O
increased	O
processor	O
complexity	O
,	O
cost	O
,	O
and	O
energy	O
consumption	O
in	O
exchange	O
for	O
faster	O
execution	O
.	O
</s>
<s>
During	O
this	O
time	O
,	O
HP	O
had	O
begun	O
to	O
believe	O
that	O
it	O
was	O
no	O
longer	O
cost-effective	O
for	O
individual	O
enterprise	O
systems	O
companies	O
such	O
as	O
itself	O
to	O
develop	O
proprietary	O
microprocessors	B-Architecture
.	O
</s>
<s>
Intel	O
had	O
also	O
been	O
researching	O
several	O
architectural	O
options	O
for	O
going	O
beyond	O
the	O
x86	B-Operating_System
ISA	O
to	O
address	O
high-end	O
enterprise	O
server	O
and	O
high-performance	O
computing	O
(	O
HPC	O
)	O
requirements	O
.	O
</s>
<s>
Intel	O
and	O
HP	O
partnered	O
in	O
1994	O
to	O
develop	O
the	O
IA-64	B-General_Concept
ISA	O
,	O
using	O
a	O
variation	O
of	O
VLIW	B-General_Concept
design	O
concepts	O
which	O
Intel	O
named	O
explicitly	B-General_Concept
parallel	I-General_Concept
instruction	I-General_Concept
computing	I-General_Concept
(	O
EPIC	B-General_Concept
)	O
.	O
</s>
<s>
Intel	O
's	O
goal	O
was	O
to	O
leverage	O
the	O
expertise	O
HP	O
had	O
developed	O
in	O
their	O
early	O
VLIW	B-General_Concept
work	O
along	O
with	O
their	O
own	O
to	O
develop	O
a	O
volume	O
product	O
line	O
targeted	O
at	O
the	O
aforementioned	O
high-end	O
systems	O
that	O
could	O
be	O
sold	O
to	O
all	O
original	O
equipment	O
manufacturers	O
(	O
OEMs	O
)	O
,	O
while	O
HP	O
wished	O
to	O
be	O
able	O
to	O
purchase	O
off-the-shelf	O
processors	O
built	O
using	O
Intel	O
's	O
volume	O
manufacturing	O
and	O
contemporary	O
process	O
technology	O
that	O
were	O
better	O
than	O
their	O
PA-RISC	O
processors	O
.	O
</s>
<s>
Intel	O
took	O
the	O
lead	O
on	O
the	O
design	O
and	O
commercialization	O
process	O
,	O
while	O
HP	O
contributes	O
to	O
the	O
ISA	O
definition	O
,	O
the	O
Merced/Itanium	O
microarchitecture	O
,	O
and	O
Itanium	B-General_Concept
2	O
.	O
</s>
<s>
The	O
original	O
goal	O
year	O
for	O
delivering	O
the	O
first	O
Itanium	B-General_Concept
family	O
product	O
,	O
Merced	O
,	O
was	O
1998	O
.	O
</s>
<s>
Intel	O
's	O
product	O
marketing	O
and	O
industry	O
engagement	O
efforts	O
were	O
substantial	O
and	O
achieved	O
design	O
wins	O
with	O
the	O
majority	O
of	O
enterprise	O
server	O
OEMs	O
,	O
including	O
those	O
based	O
on	O
RISC	B-Architecture
processors	I-Architecture
at	O
the	O
time	O
.	O
</s>
<s>
Compaq	O
and	O
Silicon	O
Graphics	O
decided	O
to	O
abandon	O
further	O
development	O
of	O
the	O
Alpha	B-Device
and	O
MIPS	B-Device
architectures	I-Device
respectively	O
in	O
favor	O
of	O
migrating	O
to	O
IA-64	B-General_Concept
.	O
</s>
<s>
By	O
1997	O
,	O
it	O
was	O
apparent	O
that	O
the	O
IA-64	B-General_Concept
architecture	O
and	O
the	O
compiler	B-Language
were	O
much	O
more	O
difficult	O
to	O
implement	O
than	O
originally	O
thought	O
,	O
and	O
the	O
delivery	O
of	O
Itanium	B-General_Concept
began	O
slipping	O
.	O
</s>
<s>
Since	O
Itanium	B-General_Concept
was	O
the	O
first	O
ever	O
EPIC	B-General_Concept
processor	O
,	O
the	O
development	O
effort	O
encountered	O
more	O
unanticipated	O
problems	O
than	O
the	O
team	O
was	O
accustomed	O
to	O
.	O
</s>
<s>
In	O
addition	O
,	O
the	O
EPIC	B-General_Concept
concept	O
depends	O
on	O
compiler	B-Language
capabilities	O
that	O
had	O
never	O
been	O
implemented	O
before	O
,	O
so	O
more	O
research	O
was	O
needed	O
.	O
</s>
<s>
Several	O
groups	O
developed	O
operating	O
systems	O
for	O
the	O
architecture	O
,	O
including	O
Microsoft	B-Application
Windows	I-Application
,	O
Unix	B-Application
and	O
Unix-like	B-Operating_System
systems	I-Operating_System
such	O
as	O
Linux	B-Application
,	O
HP-UX	B-Application
,	O
FreeBSD	B-Operating_System
,	O
Solaris	B-Application
,	O
Tru64	B-Operating_System
UNIX	I-Operating_System
,	O
and	O
Monterey/64	B-Operating_System
(	O
the	O
last	O
three	O
were	O
canceled	O
before	O
reaching	O
the	O
market	O
)	O
.	O
</s>
<s>
In	O
1999	O
,	O
Intel	O
led	O
the	O
formation	O
of	O
an	O
open-source	O
industry	O
consortium	O
to	O
port	O
Linux	B-Application
to	O
IA-64	B-General_Concept
they	O
named	O
"	O
Trillium	O
"	O
(	O
and	O
later	O
renamed	O
"	O
Trillian	O
"	O
due	O
to	O
a	O
trademark	O
issue	O
)	O
,	O
which	O
was	O
led	O
by	O
Intel	O
and	O
included	O
Caldera	O
Systems	O
,	O
CERN	O
,	O
Cygnus	O
Solutions	O
,	O
Hewlett-Packard	O
,	O
IBM	O
,	O
Red	O
Hat	O
,	O
SGI	O
,	O
SuSE	O
,	O
TurboLinux	O
and	O
VA	O
Linux	B-Application
Systems	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
a	O
working	O
IA-64	B-General_Concept
Linux	B-Application
was	O
delivered	O
ahead	O
of	O
schedule	O
and	O
was	O
the	O
first	O
OS	O
to	O
run	O
on	O
the	O
new	O
Itanium	B-General_Concept
processors	O
.	O
</s>
<s>
Intel	O
announced	O
the	O
official	O
name	O
of	O
the	O
processor	O
,	O
Itanium	B-General_Concept
,	O
on	O
October	O
4	O
,	O
1999	O
.	O
</s>
<s>
Within	O
hours	O
,	O
the	O
name	O
Itanic	O
had	O
been	O
coined	O
on	O
a	O
Usenet	B-Application
newsgroup	O
as	O
a	O
pun	B-Application
on	O
the	O
name	O
Titanic	O
,	O
the	O
"	O
unsinkable	O
"	O
ocean	O
liner	O
that	O
sank	O
on	O
its	O
maiden	O
voyage	O
in	O
1912	O
.	O
</s>
<s>
The	O
very	O
next	O
day	O
on	O
5th	O
October	O
1999	O
,	O
AMD	O
announced	O
their	O
plans	O
to	O
extend	O
Intel	O
's	O
x86	B-Operating_System
instruction	B-General_Concept
set	I-General_Concept
to	O
include	O
a	O
fully	O
downward	O
compatible	O
64-bit	B-Device
mode	O
–	O
additionally	O
revealing	O
AMD	O
's	O
newly	O
coming	O
x86	B-Operating_System
64-bit	B-Device
architecture	O
,	O
which	O
the	O
company	O
already	O
worked	O
on	O
,	O
to	O
be	O
incorporated	O
into	O
AMD	O
's	O
upcoming	O
eighth-generation	O
microprocessor	B-Architecture
,	O
code-named	O
SledgeHammer	O
.	O
</s>
<s>
As	O
AMD	O
was	O
never	O
invited	O
to	O
be	O
a	O
contributing	O
party	O
for	O
the	O
IA-64	B-General_Concept
architecture	O
and	O
any	O
kind	O
of	O
licensing	O
seemed	O
unlikely	O
,	O
AMD	O
's	O
AMD64	B-Device
architecture-extension	O
was	O
positioned	O
from	O
the	O
beginning	O
as	O
an	O
evolutionary	O
way	O
to	O
add	O
64-bit	B-Device
computing	I-Device
capabilities	O
to	O
the	O
existing	O
x86	B-Operating_System
architecture	I-Operating_System
,	O
while	O
still	O
supporting	O
legacy	O
32-bit	B-Device
x86	I-Device
code	B-Language
–	O
as	O
opposed	O
to	O
Intel	O
's	O
approach	O
of	O
creating	O
an	O
entirely	O
new	O
,	O
completely	O
x86-incompatible	O
64-bit	B-Device
architecture	I-Device
with	O
IA-64	B-General_Concept
.	O
</s>
<s>
By	O
the	O
time	O
Itanium	B-General_Concept
was	O
released	O
in	O
June	O
2001	O
,	O
its	O
performance	O
was	O
not	O
superior	O
to	O
competing	O
RISC	B-Architecture
and	O
CISC	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
HP	O
and	O
Intel	O
brought	O
the	O
next-generation	O
Itanium	B-General_Concept
2	O
processor	O
to	O
market	O
a	O
year	O
later	O
.	O
</s>
<s>
The	O
Itanium	B-General_Concept
2	O
processor	O
was	O
released	O
in	O
2002	O
.	O
</s>
<s>
It	O
relieved	O
many	O
of	O
the	O
performance	O
problems	O
of	O
the	O
original	O
Itanium	B-General_Concept
processor	O
,	O
which	O
were	O
mostly	O
caused	O
by	O
an	O
inefficient	O
memory	O
subsystem	O
.	O
</s>
<s>
In	O
2003	O
,	O
AMD	O
released	O
the	O
Opteron	B-General_Concept
,	O
which	O
implemented	O
its	O
own	O
64-bit	B-Device
architecture	I-Device
(	O
x86-64	B-Device
)	O
.	O
</s>
<s>
Opteron	B-General_Concept
gained	O
rapid	O
acceptance	O
in	O
the	O
enterprise	O
server	O
space	O
because	O
it	O
provided	O
an	O
easy	O
upgrade	O
from	O
x86	B-Operating_System
.	O
</s>
<s>
Intel	O
responded	O
by	O
implementing	O
x86-64	B-Device
(	O
as	O
Em64t	B-Device
)	O
in	O
its	O
Xeon	B-Device
microprocessors	B-Architecture
in	O
2004	O
.	O
</s>
<s>
In	O
November	O
2005	O
,	O
the	O
major	O
Itanium	B-General_Concept
server	O
manufacturers	O
joined	O
with	O
Intel	O
and	O
a	O
number	O
of	O
software	O
vendors	O
to	O
form	O
the	O
Itanium	B-General_Concept
Solutions	O
Alliance	O
to	O
promote	O
the	O
architecture	O
and	O
accelerate	O
software	O
porting	O
.	O
</s>
<s>
In	O
2006	O
,	O
Intel	O
delivered	O
Montecito	B-Device
(	O
marketed	O
as	O
the	O
Itanium	B-General_Concept
2	O
9000	O
series	O
)	O
,	O
a	O
dual-core	O
processor	O
that	O
roughly	O
doubled	O
performance	O
and	O
decreased	O
energy	O
consumption	O
by	O
about	O
20	O
percent	O
.	O
</s>
<s>
The	O
Itanium	B-General_Concept
9300	I-General_Concept
series	I-General_Concept
processor	O
,	O
codenamed	B-Architecture
Tukwila	B-General_Concept
,	O
was	O
released	O
on	O
8	O
February	O
2010	O
with	O
greater	O
performance	O
and	O
memory	O
capacity	O
.	O
</s>
<s>
Tukwila	B-General_Concept
had	O
originally	O
been	O
slated	O
for	O
release	O
in	O
2007	O
.	O
</s>
<s>
The	O
device	O
uses	O
a	O
65nm	O
process	O
,	O
includes	O
two	O
to	O
four	O
cores	O
,	O
up	O
to	O
24MB	O
on-die	O
caches	O
,	O
Hyper-Threading	B-Operating_System
technology	I-Operating_System
and	O
integrated	O
memory	O
controllers	O
.	O
</s>
<s>
Tukwila	B-General_Concept
also	O
implements	O
Intel	B-Architecture
QuickPath	I-Architecture
Interconnect	I-Architecture
(	O
QPI	B-Architecture
)	O
to	O
replace	O
the	O
Itanium	B-General_Concept
bus-based	O
architecture	O
.	O
</s>
<s>
With	O
QuickPath	B-Architecture
,	O
the	O
processor	O
has	O
integrated	O
memory	O
controllers	O
and	O
interfaces	O
the	O
memory	O
directly	O
,	O
using	O
QPI	B-Architecture
interfaces	I-Architecture
to	O
directly	O
connect	O
to	O
other	O
processors	O
and	O
I/O	O
hubs	O
.	O
</s>
<s>
QuickPath	B-Architecture
is	O
also	O
used	O
on	O
Intel	O
processors	O
using	O
the	O
Nehalem	B-Device
microarchitecture	I-Device
,	O
making	O
it	O
probable	O
that	O
Tukwila	B-General_Concept
and	O
Nehalem	B-Device
will	O
be	O
able	O
to	O
use	O
the	O
same	O
chipsets	B-Device
.	O
</s>
<s>
Tukwila	B-General_Concept
incorporates	O
four	O
memory	O
controllers	O
,	O
each	O
of	O
which	O
supports	O
multiple	O
DDR3	O
DIMMs	B-General_Concept
via	O
a	O
separate	O
memory	O
controller	O
,	O
</s>
<s>
much	O
like	O
the	O
Nehalem-based	O
Xeon	B-Device
processor	O
code-named	O
Beckton	O
.	O
</s>
<s>
The	O
Itanium	B-General_Concept
9500	O
series	O
processor	O
,	O
codenamed	B-Architecture
Poulson	O
,	O
is	O
the	O
follow-on	O
processor	O
to	O
Tukwila	B-General_Concept
features	O
eight	O
cores	O
,	O
has	O
a	O
12-wide	O
issue	O
architecture	O
,	O
multithreading	O
enhancements	O
,	O
and	O
new	O
instructions	O
to	O
take	O
advantage	O
of	O
parallelism	O
,	O
especially	O
in	O
virtualization	B-General_Concept
.	O
</s>
<s>
The	O
Poulson	O
L3	O
cache	B-General_Concept
size	O
is	O
32MB	O
.	O
</s>
<s>
L2	O
cache	B-General_Concept
size	O
is	O
6MB	O
,	O
512IKB	O
,	O
256DKB	O
per	O
core	O
.	O
</s>
<s>
Die	O
size	O
is	O
544mm²	O
,	O
less	O
than	O
its	O
predecessor	O
Tukwila	B-General_Concept
(	O
698.75mm²	O
)	O
.	O
</s>
<s>
At	O
ISSCC	O
2011	O
,	O
Intel	O
presented	O
a	O
paper	O
called	O
,	O
"	O
A	O
32nm	O
3.1	O
Billion	O
Transistor	O
12-Wide-Issue	O
Itanium	B-General_Concept
Processor	O
for	O
Mission	O
Critical	O
Servers.	O
"	O
</s>
<s>
Given	O
Intel	O
's	O
history	O
of	O
disclosing	O
details	O
about	O
Itanium	B-General_Concept
microprocessors	I-General_Concept
at	O
ISSCC	O
,	O
this	O
paper	O
most	O
likely	O
refers	O
to	O
Poulson	O
.	O
</s>
<s>
New	O
information	O
presents	O
improvements	O
in	O
multithreading	O
,	O
resiliency	O
improvements	O
(	O
Instruction	O
Replay	O
RAS	O
)	O
and	O
few	O
new	O
instructions	O
(	O
thread	O
priority	O
,	O
integer	O
instruction	O
,	O
cache	B-General_Concept
prefetching	O
,	O
data	O
access	O
hints	O
)	O
.	O
</s>
<s>
Intel	O
has	O
extensively	O
documented	O
the	O
Itanium	B-General_Concept
instruction	B-General_Concept
set	I-General_Concept
and	O
the	O
technical	O
press	O
has	O
provided	O
overviews	O
.	O
</s>
<s>
Intel	O
later	O
called	O
it	O
IA-64	B-General_Concept
,	O
then	O
Itanium	B-General_Concept
Processor	O
Architecture	O
(	O
IPA	O
)	O
,	O
before	O
settling	O
on	O
Intel	B-General_Concept
Itanium	I-General_Concept
Architecture	I-General_Concept
,	O
but	O
it	O
is	O
still	O
widely	O
referred	O
to	O
as	O
IA-64	B-General_Concept
.	O
</s>
<s>
It	O
is	O
a	O
64-bit	B-Device
register-rich	O
explicitly	O
parallel	O
architecture	O
.	O
</s>
<s>
The	O
base	O
data	O
word	O
is	O
64	B-Device
bits	I-Device
,	O
byte-addressable	O
.	O
</s>
<s>
The	O
logical	B-General_Concept
address	I-General_Concept
space	O
is	O
264	O
bytes	O
.	O
</s>
<s>
The	O
architecture	O
implements	O
predication	B-General_Concept
,	O
speculation	B-General_Concept
,	O
and	O
branch	B-General_Concept
prediction	I-General_Concept
.	O
</s>
<s>
It	O
uses	O
variable-sized	O
register	B-General_Concept
windowing	I-General_Concept
for	O
parameter	O
passing	O
.	O
</s>
<s>
Speculation	B-General_Concept
,	O
prediction	O
,	O
predication	B-General_Concept
,	O
and	O
renaming	O
are	O
under	O
control	O
of	O
the	O
compiler	B-Language
:	O
each	O
instruction	O
word	O
includes	O
extra	O
bits	O
for	O
this	O
.	O
</s>
<s>
The	O
architecture	O
implements	O
a	O
large	O
number	O
of	O
registers	B-General_Concept
:	O
</s>
<s>
128	O
general	O
integer	O
registers	B-General_Concept
,	O
which	O
are	O
64-bit	B-Device
plus	O
one	O
trap	B-General_Concept
bit	I-General_Concept
(	O
"	O
NaT	O
"	O
,	O
which	O
stands	O
for	O
"	O
not	O
a	O
thing	O
"	O
)	O
used	O
for	O
speculative	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
32	O
of	O
these	O
are	O
static	O
,	O
the	O
other	O
96	O
are	O
stacked	O
using	O
variably-sized	O
register	B-General_Concept
windows	I-General_Concept
,	O
or	O
rotating	O
for	O
pipelined	O
loops	O
.	O
</s>
<s>
128	O
floating-point	B-Algorithm
registers	B-General_Concept
.	O
</s>
<s>
The	O
floating-point	B-Algorithm
registers	B-General_Concept
are	O
82	O
bits	O
long	O
to	O
preserve	O
precision	O
for	O
intermediate	O
results	O
.	O
</s>
<s>
Instead	O
of	O
a	O
dedicated	O
"	O
NaT	O
"	O
trap	B-General_Concept
bit	I-General_Concept
like	O
the	O
integer	O
registers	B-General_Concept
,	O
floating-point	B-Algorithm
registers	B-General_Concept
have	O
a	O
trap	O
value	O
called	O
"	O
NaTVal	O
"	O
(	O
"	O
Not	O
a	O
Thing	O
Value	O
"	O
)	O
,	O
similar	O
to	O
(	O
but	O
distinct	O
from	O
)	O
NaN	O
.	O
</s>
<s>
These	O
also	O
have	O
32	O
static	O
registers	B-General_Concept
and	O
96	O
windowed	O
or	O
rotating	O
registers	B-General_Concept
.	O
</s>
<s>
64	O
one-bit	O
predicate	O
registers	B-General_Concept
.	O
</s>
<s>
These	O
also	O
have	O
32	O
static	O
registers	B-General_Concept
and	O
96	O
windowed	O
or	O
rotating	O
registers	B-General_Concept
.	O
</s>
<s>
8	O
branch	O
registers	B-General_Concept
,	O
for	O
the	O
addresses	O
of	O
indirect	O
jumps	O
.	O
</s>
<s>
128	O
special	O
purpose	O
(	O
or	O
"	O
application	O
"	O
)	O
registers	B-General_Concept
,	O
which	O
are	O
mostly	O
of	O
interest	O
to	O
the	O
kernel	O
and	O
not	O
ordinary	O
applications	O
.	O
</s>
<s>
For	O
example	O
,	O
one	O
register	O
called	O
bsp	O
points	O
to	O
the	O
second	O
stack	O
,	O
which	O
is	O
where	O
the	O
hardware	O
will	O
automatically	O
spill	O
registers	B-General_Concept
when	O
the	O
register	B-General_Concept
window	I-General_Concept
wraps	O
around	O
.	O
</s>
<s>
Those	O
types	O
are	O
M-unit	O
(	O
memory	O
instructions	O
)	O
,	O
I-unit	O
(	O
integer	O
ALU	O
,	O
non-ALU	O
integer	O
,	O
or	O
long	O
immediate	O
extended	O
instructions	O
)	O
,	O
F-unit	O
(	O
floating-point	B-Algorithm
instructions	O
)	O
,	O
or	O
B-unit	O
(	O
branch	O
or	O
long	O
branch	O
extended	O
instructions	O
)	O
.	O
</s>
<s>
The	O
IA-64	B-General_Concept
assembly	O
language	O
and	O
instruction	O
format	O
was	O
deliberately	O
designed	O
to	O
be	O
written	O
mainly	O
by	O
compilers	B-Language
,	O
not	O
by	O
humans	O
.	O
</s>
<s>
The	O
fetch	O
mechanism	O
can	O
read	O
up	O
to	O
two	O
bundles	O
per	O
clock	O
from	O
the	O
L1	O
cache	B-General_Concept
into	O
the	O
pipeline	O
.	O
</s>
<s>
When	O
the	O
compiler	B-Language
can	O
take	O
maximum	O
advantage	O
of	O
this	O
,	O
the	O
processor	O
can	O
execute	O
six	O
instructions	O
per	O
clock	O
cycle	O
.	O
</s>
<s>
Each	O
unit	O
can	O
execute	O
a	O
particular	O
subset	O
of	O
the	O
instruction	B-General_Concept
set	I-General_Concept
,	O
and	O
each	O
unit	O
executes	O
at	O
a	O
rate	O
of	O
one	O
instruction	O
per	O
cycle	O
unless	O
execution	O
stalls	O
waiting	O
for	O
data	O
.	O
</s>
<s>
While	O
not	O
all	O
units	O
in	O
a	O
group	O
execute	O
identical	O
subsets	O
of	O
the	O
instruction	B-General_Concept
set	I-General_Concept
,	O
common	O
instructions	O
can	O
be	O
executed	O
in	O
multiple	O
units	O
.	O
</s>
<s>
Ideally	O
,	O
the	O
compiler	B-Language
can	O
often	O
group	O
instructions	O
into	O
sets	O
of	O
six	O
that	O
can	O
execute	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
Since	O
the	O
floating-point	B-Algorithm
units	O
implement	O
a	O
multiply	B-Algorithm
–	I-Algorithm
accumulate	I-Algorithm
operation	I-Algorithm
,	O
a	O
single	O
floating-point	B-Algorithm
instruction	O
can	O
perform	O
the	O
work	O
of	O
two	O
instructions	O
when	O
the	O
application	O
requires	O
a	O
multiply	O
followed	O
by	O
an	O
add	O
:	O
this	O
is	O
very	O
common	O
in	O
scientific	O
processing	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
800MHz	O
Itanium	B-General_Concept
had	O
a	O
theoretical	O
rating	O
of	O
3.2GFLOPS	O
and	O
the	O
fastest	O
Itanium	B-General_Concept
2	O
,	O
at	O
1.67GHz	O
,	O
was	O
rated	O
at	O
6.67GFLOPS	O
.	O
</s>
<s>
The	O
densest	O
possible	O
code	B-Language
requires	O
42.6	O
bits	O
per	O
instruction	O
,	O
compared	O
to	O
32	O
bits	O
per	O
instruction	O
on	O
traditional	O
RISC	B-Architecture
processors	I-Architecture
of	O
the	O
time	O
,	O
and	O
no-ops	O
due	O
to	O
wasted	O
slots	O
further	O
decrease	O
the	O
density	O
of	O
code	B-Language
.	O
</s>
<s>
Additional	O
instructions	O
for	O
speculative	O
loads	O
and	O
hints	O
for	O
branches	O
and	O
cache	B-General_Concept
are	O
difficult	O
to	O
generate	O
optimally	O
,	O
even	O
with	O
modern	O
compilers	B-Language
.	O
</s>
<s>
From	O
2002	O
to	O
2006	O
,	O
Itanium	B-General_Concept
2	O
processors	O
shared	O
a	O
common	O
cache	B-General_Concept
hierarchy	O
.	O
</s>
<s>
They	O
had	O
16KB	O
of	O
Level	O
1	O
instruction	O
cache	B-General_Concept
and	O
16KB	O
of	O
Level	O
1	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
L2	O
cache	B-General_Concept
was	O
unified	O
(	O
both	O
instruction	O
and	O
data	O
)	O
and	O
is	O
256KB	O
.	O
</s>
<s>
The	O
Level	O
3	O
cache	B-General_Concept
was	O
also	O
unified	O
and	O
varied	O
in	O
size	O
from	O
1.5MB	O
to	O
24MB	O
.	O
</s>
<s>
The	O
256KB	O
L2	O
cache	B-General_Concept
contains	O
sufficient	O
logic	O
to	O
handle	O
semaphore	B-Operating_System
operations	O
without	O
disturbing	O
the	O
main	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
.	O
</s>
<s>
Main	O
memory	O
is	O
accessed	O
through	O
a	O
bus	B-General_Concept
to	O
an	O
off-chip	O
chipset	B-Device
.	O
</s>
<s>
The	O
Itanium	B-General_Concept
2	O
bus	B-General_Concept
was	O
initially	O
called	O
the	O
McKinley	O
bus	B-General_Concept
,	O
but	O
is	O
now	O
usually	O
referred	O
to	O
as	O
the	O
Itanium	B-General_Concept
bus	B-General_Concept
.	O
</s>
<s>
The	O
speed	O
of	O
the	O
bus	B-General_Concept
has	O
increased	O
steadily	O
with	O
new	O
processor	O
releases	O
.	O
</s>
<s>
Itanium	B-General_Concept
processors	O
released	O
prior	O
to	O
2006	O
had	O
hardware	O
support	O
for	O
the	O
IA-32	B-Device
architecture	O
to	O
permit	O
support	O
for	O
legacy	O
server	O
applications	O
,	O
but	O
performance	O
for	O
IA-32	B-Device
code	B-Language
was	O
much	O
worse	O
than	O
for	O
native	B-Language
code	I-Language
and	O
also	O
worse	O
than	O
the	O
performance	O
of	O
contemporaneous	O
x86	B-Operating_System
processors	O
.	O
</s>
<s>
In	O
2005	O
,	O
Intel	O
developed	O
the	O
IA-32	B-Device
Execution	I-Device
Layer	I-Device
(	O
IA-32	B-Device
EL	I-Device
)	O
,	O
a	O
software	O
emulator	O
that	O
provides	O
better	O
performance	O
.	O
</s>
<s>
With	O
Montecito	B-Device
,	O
Intel	O
therefore	O
eliminated	O
hardware	O
support	O
for	O
IA-32	B-Device
code	B-Language
.	O
</s>
<s>
In	O
2006	O
,	O
with	O
the	O
release	O
of	O
Montecito	B-Device
,	O
Intel	O
made	O
a	O
number	O
of	O
enhancements	O
to	O
the	O
basic	O
processor	O
architecture	O
including	O
:	O
</s>
<s>
Intel	O
calls	O
this	O
"	O
coarse	O
multithreading	O
"	O
to	O
distinguish	O
it	O
from	O
the	O
"	O
hyper-threading	B-Operating_System
technology	I-Operating_System
"	O
Intel	O
integrated	O
into	O
some	O
x86	B-Operating_System
and	O
x86-64	B-Device
microprocessors	B-Architecture
.	O
</s>
<s>
Hardware	O
support	O
for	O
virtualization	B-General_Concept
:	O
Intel	O
added	O
Intel	O
Virtualization	B-General_Concept
Technology	O
(	O
Intel	O
VT-i	O
)	O
,	O
which	O
provides	O
hardware	O
assists	O
for	O
core	O
virtualization	B-General_Concept
functions	O
.	O
</s>
<s>
Virtualization	B-General_Concept
allows	O
a	O
software	O
"	O
hypervisor	B-Operating_System
"	O
to	O
run	O
multiple	O
operating	O
system	O
instances	O
on	O
the	O
processor	O
concurrently	O
.	O
</s>
<s>
Cache	B-General_Concept
enhancements	O
:	O
Montecito	B-Device
added	O
a	O
split	O
L2	O
cache	B-General_Concept
,	O
which	O
included	O
a	O
dedicated	O
1MB	O
L2	O
cache	B-General_Concept
for	O
instructions	O
.	O
</s>
<s>
The	O
original	O
256KB	O
L2	O
cache	B-General_Concept
was	O
converted	O
to	O
a	O
dedicated	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Montecito	B-Device
also	O
included	O
up	O
to	O
12MB	O
of	O
on-die	O
L3	O
cache	B-General_Concept
.	O
</s>
<s>
See	O
Chipsets	B-Device
...	O
Other	O
markets	O
.	O
</s>
