<s>
HyperTransport	B-Device
(	O
HT	O
)	O
,	O
formerly	O
known	O
as	O
Lightning	B-Device
Data	I-Device
Transport	I-Device
,	O
is	O
a	O
technology	O
for	O
interconnection	O
of	O
computer	O
processors	O
.	O
</s>
<s>
It	O
is	O
a	O
bidirectional	O
serial/parallel	O
high-bandwidth	O
,	O
low-latency	O
point-to-point	B-Architecture
link	I-Architecture
that	O
was	O
introduced	O
on	O
April	O
2	O
,	O
2001	O
.	O
</s>
<s>
The	O
HyperTransport	B-Architecture
Consortium	I-Architecture
is	O
in	O
charge	O
of	O
promoting	O
and	O
developing	O
HyperTransport	B-Device
technology	O
.	O
</s>
<s>
HyperTransport	B-Device
is	O
best	O
known	O
as	O
the	O
system	B-Architecture
bus	I-Architecture
architecture	O
of	O
AMD	O
central	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
(	O
CPUs	B-General_Concept
)	O
from	O
Athlon	O
64	O
through	O
AMD	O
FX	O
and	O
the	O
associated	O
motherboard	B-Device
chipsets	O
.	O
</s>
<s>
HyperTransport	B-Device
has	O
also	O
been	O
used	O
by	O
IBM	O
and	O
Apple	O
for	O
the	O
Power	B-Device
Mac	I-Device
G5	I-Device
machines	O
,	O
as	O
well	O
as	O
a	O
number	O
of	O
modern	O
MIPS	B-Device
systems	O
.	O
</s>
<s>
The	O
current	O
specification	O
HTX	O
3.1	O
remained	O
competitive	O
for	O
2014	O
high-speed	O
(	O
2666	O
and	O
3200MT/s	O
or	O
about	O
10.4GB/s	O
and	O
12.8GB/s	O
)	O
DDR4	O
RAM	B-Architecture
and	O
slower	O
(	O
around	O
1GB/s	O
similar	O
to	O
high	O
end	O
PCIe	O
SSDs	O
ULLtraDIMM	B-Device
flash	O
RAM	B-Architecture
)	O
technology	O
—	O
a	O
wider	O
range	O
of	O
RAM	B-Architecture
speeds	O
on	O
a	O
common	O
CPU	O
bus	O
than	O
any	O
Intel	O
front-side	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
Intel	O
technologies	O
require	O
each	O
speed	O
range	O
of	O
RAM	B-Architecture
to	O
have	O
its	O
own	O
interface	O
,	O
resulting	O
in	O
a	O
more	O
complex	O
motherboard	B-Device
layout	O
but	O
with	O
fewer	O
bottlenecks	O
.	O
</s>
<s>
Beyond	O
that	O
DDR4	O
RAM	B-Architecture
may	O
require	O
two	O
or	O
more	O
HTX	O
3.1	O
buses	O
diminishing	O
its	O
value	O
as	O
unified	O
transport	O
.	O
</s>
<s>
HyperTransport	B-Device
comes	O
in	O
four	O
versions	O
—	O
1.x	O
,	O
2.0	O
,	O
3.0	O
,	O
and	O
3.1	O
—	O
which	O
run	O
from	O
200MHz	O
to	O
3.2GHz	O
.	O
</s>
<s>
The	O
operating	O
frequency	O
is	O
autonegotiated	O
with	O
the	O
motherboard	B-Device
chipset	O
(	O
North	O
Bridge	O
)	O
in	O
current	O
computing	O
.	O
</s>
<s>
HyperTransport	B-Device
supports	O
an	O
autonegotiated	O
bit	O
width	O
,	O
ranging	O
from	O
2	O
to	O
32bits	O
per	O
link	O
;	O
there	O
are	O
two	O
unidirectional	O
links	O
per	O
HyperTransport	B-Device
bus	O
.	O
</s>
<s>
With	O
the	O
advent	O
of	O
version	O
3.1	O
,	O
using	O
full	O
32-bit	O
links	O
and	O
utilizing	O
the	O
full	O
HyperTransport	B-Device
3.1	O
specification	O
's	O
operating	O
frequency	O
,	O
the	O
theoretical	O
transfer	O
rate	O
is	O
25.6GB/s	O
(	O
3.2GHz	O
×	O
2	O
transfers	O
per	O
clock	O
cycle	O
×	O
32bits	O
per	O
link	O
)	O
per	O
direction	O
,	O
or	O
51.2GB/s	O
aggregated	O
throughput	O
,	O
making	O
it	O
faster	O
than	O
most	O
existing	O
bus	O
standard	O
for	O
PC	O
workstations	O
and	O
servers	O
as	O
well	O
as	O
making	O
it	O
faster	O
than	O
most	O
bus	O
standards	O
for	O
high-performance	O
computing	O
and	O
networking	O
.	O
</s>
<s>
Links	O
of	O
various	O
widths	O
can	O
be	O
mixed	O
together	O
in	O
a	O
single	O
system	O
configuration	O
as	O
in	O
one	O
16-bit	B-Device
link	O
to	O
another	O
CPU	O
and	O
one	O
8-bit	O
link	O
to	O
a	O
peripheral	O
device	O
,	O
which	O
allows	O
for	O
a	O
wider	O
interconnect	O
between	O
CPUs	B-General_Concept
,	O
and	O
a	O
lower	O
bandwidth	O
interconnect	O
to	O
peripherals	O
as	O
appropriate	O
.	O
</s>
<s>
It	O
also	O
supports	O
link	O
splitting	O
,	O
where	O
a	O
single	O
16-bit	B-Device
link	O
can	O
be	O
divided	O
into	O
two	O
8-bit	O
links	O
.	O
</s>
<s>
The	O
technology	O
also	O
typically	O
has	O
lower	O
latency	B-General_Concept
than	O
other	O
solutions	O
due	O
to	O
its	O
lower	O
overhead	O
.	O
</s>
<s>
Electrically	O
,	O
HyperTransport	B-Device
is	O
similar	O
to	O
low-voltage	B-Architecture
differential	I-Architecture
signaling	I-Architecture
(	O
LVDS	B-Architecture
)	O
operating	O
at	O
1.2V	O
.	O
</s>
<s>
HyperTransport	B-Device
2.0	O
added	O
post-cursor	O
transmitter	O
deemphasis	B-Algorithm
.	O
</s>
<s>
HyperTransport	B-Device
3.0	O
added	O
scrambling	O
and	O
receiver	O
phase	O
alignment	O
as	O
well	O
as	O
optional	O
transmitter	O
precursor	O
deemphasis	B-Algorithm
.	O
</s>
<s>
HyperTransport	B-Device
is	O
packet-based	O
,	O
where	O
each	O
packet	B-Protocol
consists	O
of	O
a	O
set	O
of	O
32-bit	O
words	O
,	O
regardless	O
of	O
the	O
physical	O
width	O
of	O
the	O
link	O
.	O
</s>
<s>
The	O
first	O
word	O
in	O
a	O
packet	B-Protocol
always	O
contains	O
a	O
command	O
field	O
.	O
</s>
<s>
Many	O
packets	B-Protocol
contain	O
a	O
40-bit	O
address	O
.	O
</s>
<s>
An	O
additional	O
32-bit	O
control	O
packet	B-Protocol
is	O
prepended	O
when	O
64-bit	O
addressing	O
is	O
required	O
.	O
</s>
<s>
The	O
data	O
payload	O
is	O
sent	O
after	O
the	O
control	O
packet	B-Protocol
.	O
</s>
<s>
HyperTransport	B-Device
packets	B-Protocol
enter	O
the	O
interconnect	O
in	O
segments	O
known	O
as	O
bit	O
times	O
.	O
</s>
<s>
HyperTransport	B-Device
also	O
supports	O
system	O
management	O
messaging	O
,	O
signaling	O
interrupts	O
,	O
issuing	O
probes	O
to	O
adjacent	O
devices	O
or	O
processors	O
,	O
I/O	B-General_Concept
transactions	O
,	O
and	O
general	O
data	O
transactions	O
.	O
</s>
<s>
This	O
is	O
usually	O
used	O
for	O
high	O
bandwidth	O
devices	O
such	O
as	O
uniform	B-Operating_System
memory	I-Operating_System
access	I-Operating_System
traffic	O
or	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
transfers	O
.	O
</s>
<s>
HyperTransport	B-Device
supports	O
the	O
PCI	O
consumer/producer	O
ordering	O
model	O
.	O
</s>
<s>
HyperTransport	B-Device
also	O
facilitates	O
power	O
management	O
as	O
it	O
is	O
compliant	O
with	O
the	O
Advanced	B-Device
Configuration	I-Device
and	I-Device
Power	I-Device
Interface	I-Device
specification	O
.	O
</s>
<s>
HyperTransport	B-Device
3.0	O
added	O
further	O
capabilities	O
to	O
allow	O
a	O
centralized	O
power	O
management	O
controller	O
to	O
implement	O
power	O
management	O
policies	O
.	O
</s>
<s>
The	O
primary	O
use	O
for	O
HyperTransport	B-Device
is	O
to	O
replace	O
the	O
Intel-defined	O
front-side	B-Architecture
bus	I-Architecture
,	O
which	O
is	O
different	O
for	O
every	O
type	O
of	O
Intel	O
processor	O
.	O
</s>
<s>
The	O
proprietary	O
front-side	B-Architecture
bus	I-Architecture
must	O
connect	O
through	O
adapters	O
for	O
the	O
various	O
standard	O
buses	O
,	O
like	O
AGP	B-Architecture
or	O
PCI	O
Express	O
.	O
</s>
<s>
These	O
are	O
typically	O
included	O
in	O
the	O
respective	O
controller	O
functions	O
,	O
namely	O
the	O
northbridge	B-Device
and	O
southbridge	B-Device
.	O
</s>
<s>
In	O
contrast	O
,	O
HyperTransport	B-Device
is	O
an	O
open	O
specification	O
,	O
published	O
by	O
a	O
multi-company	O
consortium	O
.	O
</s>
<s>
A	O
single	O
HyperTransport	B-Device
adapter	O
chip	O
will	O
work	O
with	O
a	O
wide	O
spectrum	O
of	O
HyperTransport	B-Device
enabled	O
microprocessors	O
.	O
</s>
<s>
AMD	O
used	O
HyperTransport	B-Device
to	O
replace	O
the	O
front-side	B-Architecture
bus	I-Architecture
in	O
their	O
Opteron	B-General_Concept
,	O
Athlon	O
64	O
,	O
Athlon	O
II	O
,	O
Sempron	O
64	O
,	O
Turion	O
64	O
,	O
Phenom	O
,	O
Phenom	O
II	O
and	O
FX	O
families	O
of	O
microprocessors	O
.	O
</s>
<s>
Another	O
use	O
for	O
HyperTransport	B-Device
is	O
as	O
an	O
interconnect	O
for	O
NUMA	B-Operating_System
multiprocessor	B-Operating_System
computers	O
.	O
</s>
<s>
AMD	O
used	O
HyperTransport	B-Device
with	O
a	O
proprietary	O
cache	B-General_Concept
coherency	I-General_Concept
extension	O
as	O
part	O
of	O
their	O
Direct	O
Connect	O
Architecture	O
in	O
their	O
Opteron	B-General_Concept
and	O
Athlon	O
64	O
FX	O
(	O
Dual	O
Socket	O
Direct	O
Connect	O
(	O
DSDC	O
)	O
Architecture	O
)	O
line	O
of	O
processors	O
.	O
</s>
<s>
Infinity	O
Fabric	O
used	O
with	O
the	O
EPYC	O
server	O
CPUs	B-General_Concept
is	O
a	O
superset	O
of	O
HyperTransport	B-Device
.	O
</s>
<s>
The	O
HORUS	B-Architecture
interconnect	I-Architecture
from	O
Newisys	O
extends	O
this	O
concept	O
to	O
larger	O
clusters	O
.	O
</s>
<s>
The	O
Aqua	O
device	O
from	O
3Leaf	O
Systems	O
virtualizes	O
and	O
interconnects	O
CPUs	B-General_Concept
,	O
memory	O
,	O
and	O
I/O	B-General_Concept
.	O
</s>
<s>
HyperTransport	B-Device
can	O
also	O
be	O
used	O
as	O
a	O
bus	O
in	O
routers	B-Protocol
and	O
switches	B-Protocol
.	O
</s>
<s>
Routers	B-Protocol
and	O
switches	B-Protocol
have	O
multiple	O
network	O
interfaces	O
,	O
and	O
must	O
forward	O
data	O
between	O
these	O
ports	O
as	O
fast	O
as	O
possible	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
four-port	O
,	O
1000Mbit/s	O
Ethernet	B-Protocol
router	I-Protocol
needs	O
a	O
maximum	O
8000Mbit/s	O
of	O
internal	O
bandwidth	O
(	O
1000Mbit/s	O
×	O
4	O
ports	O
×	O
2	O
directions	O
)	O
—	O
HyperTransport	B-Device
greatly	O
exceeds	O
the	O
bandwidth	O
this	O
application	O
requires	O
.	O
</s>
<s>
However	O
a	O
4	O
+	O
1	O
port	O
10Gb	O
router	B-Protocol
would	O
require	O
100Gbit/s	O
of	O
internal	O
bandwidth	O
.	O
</s>
<s>
Add	O
to	O
that	O
802.11ac	O
8	O
antennas	O
and	O
the	O
WiGig	O
60GHz	O
standard	O
(	O
802.11ad	O
)	O
and	O
HyperTransport	B-Device
becomes	O
more	O
feasible	O
(	O
with	O
anywhere	O
between	O
20	O
and	O
24	O
lanes	O
used	O
for	O
the	O
needed	O
bandwidth	O
)	O
.	O
</s>
<s>
The	O
issue	O
of	O
latency	B-General_Concept
and	O
bandwidth	O
between	O
CPUs	B-General_Concept
and	O
co-processors	B-General_Concept
has	O
usually	O
been	O
the	O
major	O
stumbling	O
block	O
to	O
their	O
practical	O
implementation	O
.	O
</s>
<s>
Co-processors	B-General_Concept
such	O
as	O
FPGAs	B-Architecture
have	O
appeared	O
that	O
can	O
access	O
the	O
HyperTransport	B-Device
bus	O
and	O
become	O
integrated	O
on	O
the	O
motherboard	B-Device
.	O
</s>
<s>
Current	O
generation	O
FPGAs	B-Architecture
from	O
both	O
main	O
manufacturers	O
(	O
Altera	O
and	O
Xilinx	O
)	O
directly	O
support	O
the	O
HyperTransport	B-Device
interface	O
,	O
and	O
have	O
IP	B-Architecture
Cores	I-Architecture
available	O
.	O
</s>
<s>
Companies	O
such	O
as	O
XtremeData	O
,	O
Inc	O
.	O
and	O
DRC	O
take	O
these	O
FPGAs	B-Architecture
(	O
Xilinx	O
in	O
DRC	O
's	O
case	O
)	O
and	O
create	O
a	O
module	O
that	O
allows	O
FPGAs	B-Architecture
to	O
plug	O
directly	O
into	O
the	O
Opteron	B-General_Concept
socket	O
.	O
</s>
<s>
AMD	O
started	O
an	O
initiative	O
named	O
Torrenza	B-General_Concept
on	O
September	O
21	O
,	O
2006	O
to	O
further	O
promote	O
the	O
usage	O
of	O
HyperTransport	B-Device
for	O
plug-in	O
cards	O
and	O
coprocessors	B-General_Concept
.	O
</s>
<s>
A	O
connector	O
specification	O
that	O
allows	O
a	O
slot-based	O
peripheral	O
to	O
have	O
direct	O
connection	O
to	O
a	O
microprocessor	O
using	O
a	O
HyperTransport	B-Device
interface	O
was	O
released	O
by	O
the	O
HyperTransport	B-Architecture
Consortium	I-Architecture
.	O
</s>
<s>
It	O
is	O
known	O
as	O
HyperTransport	B-Device
eXpansion	O
(	O
HTX	O
)	O
.	O
</s>
<s>
Using	O
a	O
reversed	O
instance	O
of	O
the	O
same	O
mechanical	O
connector	O
as	O
a	O
16-lane	O
PCI	O
Express	O
slot	O
(	O
plus	O
an	O
x1	O
connector	O
for	O
power	O
pins	O
)	O
,	O
HTX	O
allows	O
development	O
of	O
plug-in	O
cards	O
that	O
support	O
direct	O
access	O
to	O
a	O
CPU	O
and	O
DMA	B-General_Concept
to	O
the	O
system	O
RAM	B-Architecture
.	O
</s>
<s>
In	O
August	O
2008	O
,	O
the	O
HyperTransport	B-Architecture
Consortium	I-Architecture
released	O
HTX3	O
,	O
which	O
extends	O
the	O
clock	O
rate	O
of	O
HTX	O
to	O
2.6GHz	O
(	O
5.2GT/s	O
,	O
10.7GTi	O
,	O
5.2	O
real	O
GHz	O
data	O
rate	O
,	O
3MT/s	O
edit	O
rate	O
)	O
and	O
retains	O
backwards	O
compatibility	O
.	O
</s>
<s>
*	O
AMD	O
Athlon	O
64	O
,	O
Athlon	O
64	O
FX	O
,	O
Athlon	O
64	O
X2	O
,	O
Athlon	O
X2	O
,	O
Athlon	O
II	O
,	O
Phenom	O
,	O
Phenom	O
II	O
,	O
Sempron	O
,	O
Turion	O
series	O
and	O
later	O
use	O
one	O
16-bit	B-Device
HyperTransport	B-Device
link	O
.	O
</s>
<s>
AMD	O
Athlon	O
64	O
FX	O
(	O
1207	O
)	O
,	O
Opteron	B-General_Concept
use	O
up	O
to	O
three	O
16-bit	B-Device
HyperTransport	B-Device
links	O
.	O
</s>
<s>
Common	O
clock	O
rates	O
for	O
these	O
processor	O
links	O
are	O
800MHz	O
to	O
1GHz	O
(	O
older	O
single	O
and	O
multi	O
socket	O
systems	O
on	O
754/939/940	O
links	O
)	O
and	O
1.6GHz	O
to	O
2.0GHz	O
(	O
newer	O
single	O
socket	O
systems	O
on	O
AM2+	O
/AM3	O
links	O
—	O
most	O
newer	O
CPUs	B-General_Concept
using	O
2.0GHz	O
)	O
.	O
</s>
<s>
While	O
HyperTransport	B-Device
itself	O
is	O
capable	O
of	O
32-bit	O
width	O
links	O
,	O
that	O
width	O
is	O
not	O
currently	O
utilized	O
by	O
any	O
AMD	O
processors	O
.	O
</s>
<s>
Some	O
chipsets	O
though	O
do	O
not	O
even	O
utilize	O
the	O
16-bit	B-Device
width	O
used	O
by	O
the	O
processors	O
.	O
</s>
<s>
Those	O
include	O
the	O
Nvidia	O
nForce3	B-Device
150	O
,	O
nForce3	B-Device
Pro	O
150	O
,	O
and	O
the	O
ULi	O
M1689	O
—	O
which	O
use	O
a	O
16-bit	B-Device
HyperTransport	B-Device
downstream	O
link	O
but	O
limit	O
the	O
HyperTransport	B-Device
upstream	O
link	O
to	O
8bits	O
.	O
</s>
<s>
There	O
has	O
been	O
some	O
marketing	O
confusion	O
between	O
the	O
use	O
of	O
HT	O
referring	O
to	O
HyperTransport	B-Device
and	O
the	O
later	O
use	O
of	O
HT	O
to	O
refer	O
to	O
Intel	O
's	O
Hyper-Threading	B-Operating_System
feature	O
on	O
some	O
Pentium	O
4-based	O
and	O
the	O
newer	O
Nehalem	O
and	O
Westmere-based	O
Intel	B-Device
Core	I-Device
microprocessors	O
.	O
</s>
<s>
Hyper-Threading	B-Operating_System
is	O
officially	O
known	O
as	O
Hyper-Threading	B-Operating_System
Technology	I-Operating_System
(	O
HTT	O
)	O
or	O
HT	B-Operating_System
Technology	I-Operating_System
.	O
</s>
<s>
Because	O
of	O
this	O
potential	O
for	O
confusion	O
,	O
the	O
HyperTransport	B-Architecture
Consortium	I-Architecture
always	O
uses	O
the	O
written-out	O
form	O
:	O
"	O
HyperTransport.	O
"	O
</s>
<s>
Infinity	O
Fabric	O
(	O
IF	O
)	O
is	O
a	O
superset	O
of	O
HyperTransport	B-Device
announced	O
by	O
AMD	O
in	O
2016	O
as	O
an	O
interconnect	O
for	O
its	O
GPUs	O
and	O
CPUs	B-General_Concept
.	O
</s>
<s>
It	O
is	O
also	O
usable	O
as	O
interchip	O
interconnect	O
for	O
communication	O
between	O
CPUs	B-General_Concept
and	O
GPUs	O
(	O
for	O
Heterogeneous	B-Architecture
System	I-Architecture
Architecture	I-Architecture
)	O
,	O
an	O
arrangement	O
known	O
as	O
Infinity	O
Architecture	O
.	O
</s>
<s>
The	O
company	O
said	O
the	O
Infinity	O
Fabric	O
would	O
scale	O
from	O
30GB/s	O
to	O
512GB/s	O
,	O
and	O
be	O
used	O
in	O
the	O
Zen-based	O
CPUs	B-General_Concept
and	O
Vega	O
GPUs	O
which	O
were	O
subsequently	O
released	O
in	O
2017	O
.	O
</s>
<s>
On	O
Zen	O
and	O
Zen+	O
CPUs	B-General_Concept
,	O
the	O
"	O
SDF	O
"	O
data	O
interconnects	O
are	O
run	O
at	O
the	O
same	O
frequency	O
as	O
the	O
DRAM	O
memory	O
clock	O
(	O
MEMCLK	O
)	O
,	O
a	O
decision	O
made	O
to	O
remove	O
the	O
latency	B-General_Concept
caused	O
by	O
different	O
clock	O
speeds	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
using	O
a	O
faster	O
RAM	B-Architecture
module	O
makes	O
the	O
entire	O
bus	O
faster	O
.	O
</s>
<s>
The	O
links	O
are	O
32-bit	O
wide	O
,	O
as	O
in	O
HT	O
,	O
but	O
8	O
transfers	O
are	O
done	O
per	O
cycle	O
(	O
128-bit	O
packets	B-Protocol
)	O
compared	O
to	O
the	O
original	O
2	O
.	O
</s>
<s>
On	O
Zen	O
2	O
and	O
Zen	O
3	O
CPUs	B-General_Concept
,	O
the	O
IF	O
bus	O
is	O
on	O
a	O
separate	O
clock	O
,	O
either	O
in	O
a	O
1:1	O
or	O
2:1	O
ratio	O
to	O
the	O
DRAM	O
clock	O
,	O
because	O
of	O
Zen	O
's	O
early	O
problems	O
with	O
high-speed	O
DRAM	O
affecting	O
IF	O
speed	O
,	O
and	O
therefore	O
system	O
stability	O
.	O
</s>
