<s>
The	O
hyperSPARC	B-General_Concept
,	O
code-named	O
"	O
Pinnacle	O
"	O
,	O
is	O
a	O
microprocessor	B-Architecture
that	O
implements	O
the	O
SPARC	B-Architecture
Version	I-Architecture
8	I-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
developed	O
by	O
Ross	O
Technology	O
for	O
Cypress	O
Semiconductor	O
.	O
</s>
<s>
The	O
hyperSPARC	B-General_Concept
was	O
introduced	O
in	O
1993	O
,	O
and	O
competed	O
with	O
the	O
Sun	O
Microsystems	O
SuperSPARC	B-Device
.	O
</s>
<s>
The	O
hyperSPARC	B-General_Concept
was	O
Sun	O
Microsystem	O
's	O
primary	O
competitor	O
in	O
the	O
mid-1990s	O
.	O
</s>
<s>
When	O
Fujitsu	O
acquired	O
Ross	O
from	O
Cypress	O
,	O
the	O
hyperSPARC	B-General_Concept
was	O
considered	O
to	O
be	O
more	O
important	O
by	O
its	O
new	O
owner	O
than	O
the	O
SPARC64	B-General_Concept
developed	O
by	O
HAL	O
Computer	O
Systems	O
,	O
also	O
a	O
Fujitsu	O
subsidiary	O
,	O
a	O
view	O
which	O
was	O
shared	O
with	O
analysts	O
.	O
</s>
<s>
The	O
hyperSPARC	B-General_Concept
was	O
a	O
two-way	O
superscalar	B-General_Concept
microprocessor	B-Architecture
.	O
</s>
<s>
The	O
hyperSPARC	B-General_Concept
has	O
an	O
on-die	O
8	O
KB	O
instruction	O
cache	O
,	O
from	O
which	O
two	O
instructions	O
were	O
fetched	O
per	O
cycle	O
and	O
decoded	O
.	O
</s>
<s>
The	O
integer	O
register	B-General_Concept
file	I-General_Concept
contained	O
136	O
registers	O
,	O
providing	O
eight	O
register	B-General_Concept
windows	I-General_Concept
,	O
a	O
feature	O
defined	O
in	O
the	O
SPARC	B-Architecture
ISA	O
.	O
</s>
<s>
The	O
integer	O
unit	O
had	O
a	O
four-stage	O
pipeline	B-General_Concept
,	O
of	O
which	O
two	O
stages	O
were	O
added	O
so	O
the	O
pipeline	B-General_Concept
would	O
be	O
equal	O
to	O
all	O
non-floating-point	O
pipelines	O
.	O
</s>
<s>
Integer	O
multiply	O
and	O
divide	O
,	O
instructions	O
added	O
in	O
the	O
V8	O
version	O
of	O
the	O
SPARC	B-Architecture
architecture	O
,	O
had	O
an	O
18	O
-	O
and	O
37-cycle	O
latency	O
,	O
respectively	O
,	O
and	O
stalled	O
the	O
pipeline	B-General_Concept
until	O
they	O
were	O
completed	O
.	O
</s>
<s>
The	O
microprocessor	B-Architecture
supported	O
multiprocessing	B-Operating_System
on	O
MBus	B-Architecture
systems	O
.	O
</s>
<s>
The	O
hyperSPARC	B-General_Concept
consists	O
of	O
1.2	O
million	O
transistors	O
.	O
</s>
<s>
Later	O
iterations	O
of	O
the	O
hyperSPARC	B-General_Concept
have	O
more	O
transistors	O
due	O
to	O
new	O
features	O
,	O
and	O
were	O
ported	O
to	O
newer	O
processes	O
.	O
</s>
<s>
The	O
hyperSPARC	B-General_Concept
was	O
a	O
multi-chip	O
design	O
.	O
</s>
<s>
It	O
was	O
packaged	O
in	O
a	O
ceramic	O
multi-chip	B-Algorithm
module	I-Algorithm
(	O
MCM	O
)	O
with	O
a	O
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
PGA	O
)	O
.	O
</s>
<s>
The	O
hyperSPARC	B-General_Concept
used	O
the	O
Cypress	O
SparcSet	O
chipset	O
which	O
was	O
introduced	O
in	O
late	O
July	O
1992	O
.	O
</s>
<s>
SparcSet	O
was	O
also	O
compatible	O
with	O
other	O
SPARC	B-Architecture
microprocessors	B-Architecture
.	O
</s>
