<s>
Hyper-threading	B-Operating_System
(	O
officially	O
called	O
Hyper-Threading	B-Operating_System
Technology	I-Operating_System
or	O
HT	B-Operating_System
Technology	I-Operating_System
and	O
abbreviated	O
as	O
HTT	O
or	O
HT	O
)	O
is	O
Intel	O
's	O
proprietary	B-Device
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
implementation	O
used	O
to	O
improve	O
parallelization	B-Operating_System
of	I-Operating_System
computations	I-Operating_System
(	O
doing	O
multiple	O
tasks	O
at	O
once	O
)	O
performed	O
on	O
x86	B-Operating_System
microprocessors	I-Operating_System
.	O
</s>
<s>
It	O
was	O
introduced	O
on	O
Xeon	B-Device
server	O
processors	B-General_Concept
in	O
February	O
2002	O
and	O
on	O
Pentium	O
4	O
desktop	O
processors	B-General_Concept
in	O
November	O
2002	O
.	O
</s>
<s>
Since	O
then	O
,	O
Intel	O
has	O
included	O
this	O
technology	O
in	O
Itanium	B-General_Concept
,	O
Atom	B-Device
,	O
and	O
Core	B-Device
'	I-Device
i	I-Device
 '	I-Device
Series	I-Device
CPUs	O
,	O
among	O
others	O
.	O
</s>
<s>
For	O
each	O
processor	O
core	O
that	O
is	O
physically	O
present	O
,	O
the	O
operating	B-General_Concept
system	I-General_Concept
addresses	O
two	O
virtual	O
(	O
logical	B-General_Concept
)	O
cores	O
and	O
shares	O
the	O
workload	O
between	O
them	O
when	O
possible	O
.	O
</s>
<s>
The	O
main	O
function	O
of	O
hyper-threading	B-Operating_System
is	O
to	O
increase	O
the	O
number	O
of	O
independent	O
instructions	O
in	O
the	O
pipeline	O
;	O
it	O
takes	O
advantage	O
of	O
superscalar	B-General_Concept
architecture	I-General_Concept
,	O
in	O
which	O
multiple	O
instructions	O
operate	O
on	O
separate	O
data	O
in	B-Operating_System
parallel	I-Operating_System
.	O
</s>
<s>
With	O
HTT	O
,	O
one	O
physical	O
core	O
appears	O
as	O
two	O
processors	B-General_Concept
to	O
the	O
operating	B-General_Concept
system	I-General_Concept
,	O
allowing	O
concurrent	B-Architecture
scheduling	O
of	O
two	O
processes	B-Operating_System
per	O
core	O
.	O
</s>
<s>
In	O
addition	O
,	O
two	O
or	O
more	O
processes	B-Operating_System
can	O
use	O
the	O
same	O
resources	O
:	O
If	O
resources	O
for	O
one	O
process	O
are	O
not	O
available	O
,	O
then	O
another	O
process	O
can	O
continue	O
if	O
its	O
resources	O
are	O
available	O
.	O
</s>
<s>
In	O
addition	O
to	O
requiring	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
support	O
in	O
the	O
operating	B-General_Concept
system	I-General_Concept
,	O
hyper-threading	B-Operating_System
can	O
be	O
properly	O
utilized	O
only	O
with	O
an	O
operating	B-General_Concept
system	I-General_Concept
specifically	O
optimized	O
for	O
it	O
.	O
</s>
<s>
Hyper-Threading	B-Operating_System
Technology	I-Operating_System
is	O
a	O
form	O
of	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
technology	O
introduced	O
by	O
Intel	O
,	O
while	O
the	O
concept	O
behind	O
the	O
technology	O
has	O
been	O
patented	O
by	O
Sun	O
Microsystems	O
.	O
</s>
<s>
Architecturally	O
,	O
a	O
processor	O
with	O
Hyper-Threading	B-Operating_System
Technology	I-Operating_System
consists	O
of	O
two	O
logical	B-General_Concept
processors	B-General_Concept
per	O
core	O
,	O
each	O
of	O
which	O
has	O
its	O
own	O
processor	O
architectural	B-General_Concept
state	I-General_Concept
.	O
</s>
<s>
Each	O
logical	B-General_Concept
processor	O
can	O
be	O
individually	O
halted	O
,	O
interrupted	O
or	O
directed	O
to	O
execute	O
a	O
specified	O
thread	O
,	O
independently	O
from	O
the	O
other	O
logical	B-General_Concept
processor	O
sharing	O
the	O
same	O
physical	O
core	O
.	O
</s>
<s>
Unlike	O
a	O
traditional	O
dual-processor	O
configuration	O
that	O
uses	O
two	O
separate	O
physical	O
processors	B-General_Concept
,	O
the	O
logical	B-General_Concept
processors	B-General_Concept
in	O
a	O
hyper-threaded	B-Operating_System
core	O
share	O
the	O
execution	B-General_Concept
resources	I-General_Concept
.	O
</s>
<s>
These	O
resources	O
include	O
the	O
execution	O
engine	O
,	O
caches	O
,	O
and	O
system	O
bus	O
interface	O
;	O
the	O
sharing	O
of	O
resources	O
allows	O
two	O
logical	B-General_Concept
processors	B-General_Concept
to	O
work	O
with	O
each	O
other	O
more	O
efficiently	O
,	O
and	O
allows	O
a	O
logical	B-General_Concept
processor	O
to	O
borrow	O
resources	O
from	O
a	O
stalled	O
logical	B-General_Concept
core	O
(	O
assuming	O
both	O
logical	B-General_Concept
cores	O
are	O
associated	O
with	O
the	O
same	O
physical	O
core	O
)	O
.	O
</s>
<s>
The	O
degree	O
of	O
benefit	O
seen	O
when	O
using	O
a	O
hyper-threaded	B-Operating_System
or	O
multi	B-Architecture
core	I-Architecture
processor	O
depends	O
on	O
the	O
needs	O
of	O
the	O
software	O
,	O
and	O
how	O
well	O
it	O
and	O
the	O
operating	B-General_Concept
system	I-General_Concept
are	O
written	O
to	O
manage	O
the	O
processor	O
efficiently	O
.	O
</s>
<s>
Hyper-threading	B-Operating_System
works	O
by	O
duplicating	O
certain	O
sections	O
of	O
the	O
processor	O
—	O
those	O
that	O
store	O
the	O
architectural	B-General_Concept
state	I-General_Concept
—	O
but	O
not	O
duplicating	O
the	O
main	O
execution	B-General_Concept
resources	I-General_Concept
.	O
</s>
<s>
This	O
allows	O
a	O
hyper-threading	B-Operating_System
processor	O
to	O
appear	O
as	O
the	O
usual	O
"	O
physical	O
"	O
processor	O
and	O
an	O
extra	O
"	O
logical	B-General_Concept
"	O
processor	O
to	O
the	O
host	O
operating	B-General_Concept
system	I-General_Concept
(	O
HTT-unaware	O
operating	B-General_Concept
systems	I-General_Concept
see	O
two	O
"	O
physical	O
"	O
processors	B-General_Concept
)	O
,	O
allowing	O
the	O
operating	B-General_Concept
system	I-General_Concept
to	O
schedule	O
two	O
threads	O
or	O
processes	B-Operating_System
simultaneously	O
and	O
appropriately	O
.	O
</s>
<s>
When	O
execution	B-General_Concept
resources	I-General_Concept
would	O
not	O
be	O
used	O
by	O
the	O
current	O
task	O
in	O
a	O
processor	O
without	O
hyper-threading	B-Operating_System
,	O
and	O
especially	O
when	O
the	O
processor	O
is	O
stalled	O
,	O
a	O
hyper-threading	B-Operating_System
equipped	O
processor	O
can	O
use	O
those	O
execution	B-General_Concept
resources	I-General_Concept
to	O
execute	O
another	O
scheduled	O
task	O
.	O
</s>
<s>
(	O
The	O
processor	O
may	O
stall	O
due	O
to	O
a	O
cache	O
miss	O
,	O
branch	B-General_Concept
misprediction	I-General_Concept
,	O
or	O
data	B-Operating_System
dependency	I-Operating_System
.	O
)	O
</s>
<s>
This	O
technology	O
is	O
transparent	O
to	O
operating	B-General_Concept
systems	I-General_Concept
and	O
programs	O
.	O
</s>
<s>
The	O
minimum	O
that	O
is	O
required	O
to	O
take	O
advantage	O
of	O
hyper-threading	B-Operating_System
is	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
(	O
SMP	O
)	O
support	O
in	O
the	O
operating	B-General_Concept
system	I-General_Concept
,	O
as	O
the	O
logical	B-General_Concept
processors	B-General_Concept
appear	O
as	O
standard	O
separate	O
processors	B-General_Concept
.	O
</s>
<s>
It	O
is	O
possible	O
to	O
optimize	O
operating	B-General_Concept
system	I-General_Concept
behavior	O
on	O
multi-processor	O
hyper-threading	B-Operating_System
capable	O
systems	O
.	O
</s>
<s>
For	O
example	O
,	O
consider	O
an	O
SMP	O
system	O
with	O
two	O
physical	O
processors	B-General_Concept
that	O
are	O
both	O
hyper-threaded	B-Operating_System
(	O
for	O
a	O
total	O
of	O
four	O
logical	B-General_Concept
processors	B-General_Concept
)	O
.	O
</s>
<s>
If	O
the	O
operating	B-General_Concept
system	I-General_Concept
's	O
thread	O
scheduler	O
is	O
unaware	O
of	O
hyper-threading	B-Operating_System
,	O
it	O
will	O
treat	O
all	O
four	O
logical	B-General_Concept
processors	B-General_Concept
the	O
same	O
.	O
</s>
<s>
If	O
only	O
two	O
threads	O
are	O
eligible	O
to	O
run	O
,	O
it	O
might	O
choose	O
to	O
schedule	O
those	O
threads	O
on	O
the	O
two	O
logical	B-General_Concept
processors	B-General_Concept
that	O
happen	O
to	O
belong	O
to	O
the	O
same	O
physical	O
processor	O
;	O
that	O
processor	O
would	O
become	O
extremely	O
busy	O
while	O
the	O
other	O
would	O
idle	O
,	O
leading	O
to	O
poorer	O
performance	O
than	O
is	O
possible	O
by	O
scheduling	O
the	O
threads	O
onto	O
different	O
physical	O
processors	B-General_Concept
.	O
</s>
<s>
This	O
problem	O
can	O
be	O
avoided	O
by	O
improving	O
the	O
scheduler	O
to	O
treat	O
logical	B-General_Concept
processors	B-General_Concept
differently	O
from	O
physical	O
processors	B-General_Concept
;	O
in	O
a	O
sense	O
,	O
this	O
is	O
a	O
limited	O
form	O
of	O
the	O
scheduler	O
changes	O
that	O
are	O
required	O
for	O
NUMA	B-Operating_System
systems	O
.	O
</s>
<s>
The	O
first	O
published	O
paper	O
describing	O
what	O
is	O
now	O
known	O
as	O
hyper-threading	B-Operating_System
in	O
a	O
general	O
purpose	O
computer	O
was	O
written	O
by	O
Edward	O
S	O
.	O
Davidson	O
and	O
Leonard	O
.	O
</s>
<s>
Denelcor	O
,	O
Inc	O
.	O
introduced	O
multi-threading	B-General_Concept
with	O
the	O
Heterogeneous	B-Operating_System
Element	I-Operating_System
Processor	I-Operating_System
(	O
HEP	O
)	O
in	O
1982	O
.	O
</s>
<s>
Should	O
an	O
instruction	O
from	O
a	O
given	O
process	O
block	O
the	O
pipe	O
,	O
instructions	O
from	O
other	O
processes	B-Operating_System
would	O
continue	O
after	O
the	O
pipeline	O
drained	O
.	O
</s>
<s>
US	O
patent	O
for	O
the	O
technology	O
behind	O
hyper-threading	B-Operating_System
was	O
granted	O
to	O
Kenneth	O
Okin	O
at	O
Sun	O
Microsystems	O
in	O
November	O
1994	O
.	O
</s>
<s>
At	O
that	O
time	O
,	O
CMOS	B-Device
process	O
technology	O
was	O
not	O
advanced	O
enough	O
to	O
allow	O
for	O
a	O
cost-effective	O
implementation	O
.	O
</s>
<s>
Intel	O
implemented	O
hyper-threading	B-Operating_System
on	O
an	O
x86	B-Operating_System
architecture	I-Operating_System
processor	O
in	O
2002	O
with	O
the	O
Foster	O
MP-based	O
Xeon	B-Device
.	O
</s>
<s>
The	O
Intel	B-Device
Core	I-Device
&	O
Core	O
2	O
processor	O
lines	O
(	O
2006	O
)	O
that	O
succeeded	O
the	O
Pentium	O
4	O
model	O
line	O
did	O
n't	O
utilize	O
hyper-threading	B-Operating_System
.	O
</s>
<s>
The	O
processors	B-General_Concept
based	O
on	O
the	O
Core	B-Device
microarchitecture	I-Device
did	O
not	O
have	O
hyper-threading	B-Operating_System
because	O
the	O
Core	B-Device
microarchitecture	I-Device
was	O
a	O
descendant	O
of	O
the	O
older	O
P6	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
The	O
P6	B-Device
microarchitecture	I-Device
was	O
used	O
in	O
earlier	O
iterations	O
of	O
Pentium	O
processors	B-General_Concept
,	O
namely	O
,	O
the	O
Pentium	B-Device
Pro	I-Device
,	O
Pentium	O
II	O
and	O
Pentium	O
III	O
(	O
plus	O
their	O
Celeron	B-Device
&	O
Xeon	B-Device
derivatives	O
at	O
the	O
time	O
)	O
.	O
</s>
<s>
Intel	O
released	O
the	O
Nehalem	B-Device
microarchitecture	I-Device
(	O
Corei7	O
)	O
in	O
November	O
2008	O
,	O
in	O
which	O
hyper-threading	B-Operating_System
made	O
a	O
return	O
.	O
</s>
<s>
The	O
first	O
generation	O
Nehalem	B-Device
processors	B-General_Concept
contained	O
four	O
physical	O
cores	O
and	O
effectively	O
scaled	O
to	O
eight	O
threads	O
.	O
</s>
<s>
Earlier	O
Intel	B-Device
Atom	I-Device
cores	O
were	O
in-order	O
processors	B-General_Concept
,	O
sometimes	O
with	O
hyper-threading	B-Operating_System
ability	O
,	O
for	O
low	O
power	O
mobile	O
PCs	O
and	O
low-price	O
desktop	O
PCs	O
.	O
</s>
<s>
The	O
Itanium9300	O
launched	O
with	O
eight	O
threads	O
per	O
processor	O
(	O
two	O
threads	O
per	O
core	O
)	O
through	O
enhanced	O
hyper-threading	B-Operating_System
technology	I-Operating_System
.	O
</s>
<s>
The	O
next	O
model	O
,	O
the	O
Itanium	B-General_Concept
9500	O
(	O
Poulson	O
)	O
,	O
features	O
a	O
12-wide	O
issue	O
architecture	O
,	O
with	O
eight	O
CPU	B-Architecture
cores	I-Architecture
with	O
support	O
for	O
eight	O
more	O
virtual	O
cores	O
via	O
hyper-threading	B-Operating_System
.	O
</s>
<s>
The	O
Intel	O
Xeon5500	O
server	O
chips	O
also	O
utilize	O
two-way	O
hyper-threading	B-Operating_System
.	O
</s>
<s>
According	O
to	O
Intel	O
,	O
the	O
first	O
hyper-threading	B-Operating_System
implementation	O
used	O
only	O
5%	O
more	O
die	O
area	O
than	O
the	O
comparable	O
non-hyperthreaded	O
processor	O
,	O
but	O
the	O
performance	O
was	O
15	O
–	O
30%	O
better	O
.	O
</s>
<s>
Intel	O
also	O
claims	O
significant	O
performance	O
improvements	O
with	O
a	O
hyper-threading-enabled	O
Pentium4	O
processor	O
in	O
some	O
artificial-intelligence	O
algorithms	O
.	O
</s>
<s>
Overall	O
the	O
performance	O
history	O
of	O
hyper-threading	B-Operating_System
was	O
a	O
mixed	O
one	O
in	O
the	O
beginning	O
.	O
</s>
<s>
Hyper-Threading	B-Operating_System
can	O
improve	O
the	O
performance	O
of	O
some	O
MPI	B-Application
applications	O
,	O
but	O
not	O
all	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
performance	O
improvements	O
are	O
very	O
application-dependent	O
;	O
however	O
,	O
when	O
running	O
two	O
programs	O
that	O
require	O
full	O
attention	O
of	O
the	O
processor	O
,	O
it	O
can	O
actually	O
seem	O
like	O
one	O
or	O
both	O
of	O
the	O
programs	O
slows	O
down	O
slightly	O
when	O
Hyper-Threading	B-Operating_System
Technology	I-Operating_System
is	O
turned	O
on	O
.	O
</s>
<s>
This	O
is	O
due	O
to	O
the	O
replay	B-Device
system	I-Device
of	O
the	O
Pentium4	O
tying	O
up	O
valuable	O
execution	B-General_Concept
resources	I-General_Concept
,	O
equalizing	O
the	O
processor	O
resources	O
between	O
the	O
two	O
programs	O
,	O
which	O
adds	O
a	O
varying	O
amount	O
of	O
execution	O
time	O
.	O
</s>
<s>
The	O
Pentium4	O
"	O
Prescott	O
"	O
and	O
the	O
Xeon	B-Device
"	O
Nocona	O
"	O
processors	B-General_Concept
received	O
a	O
replay	O
queue	O
that	O
reduces	O
execution	O
time	O
needed	O
for	O
the	O
replay	B-Device
system	I-Device
and	O
completely	O
overcomes	O
the	O
performance	O
penalty	O
.	O
</s>
<s>
According	O
to	O
a	O
November	O
2009	O
analysis	O
by	O
Intel	O
,	O
performance	O
impacts	O
of	O
hyper-threading	B-Operating_System
result	O
in	O
increased	O
overall	O
latency	O
in	O
case	O
the	O
execution	O
of	O
threads	O
does	O
not	O
result	O
in	O
significant	O
overall	O
throughput	O
gains	O
,	O
which	O
vary	O
by	O
the	O
application	O
.	O
</s>
<s>
In	O
other	O
words	O
,	O
overall	O
processing	O
latency	O
is	O
significantly	O
increased	O
due	O
to	O
hyper-threading	B-Operating_System
,	O
with	O
the	O
negative	O
effects	O
becoming	O
smaller	O
as	O
there	O
are	O
more	O
simultaneous	O
threads	O
that	O
can	O
effectively	O
use	O
the	O
additional	O
hardware	O
resource	O
utilization	O
provided	O
by	O
hyper-threading	B-Operating_System
.	O
</s>
<s>
A	O
similar	O
performance	O
analysis	O
is	O
available	O
for	O
the	O
effects	O
of	O
hyper-threading	B-Operating_System
when	O
used	O
to	O
handle	O
tasks	O
related	O
to	O
managing	O
network	O
traffic	O
,	O
such	O
as	O
for	O
processing	O
interrupt	B-General_Concept
requests	I-General_Concept
generated	O
by	O
network	B-Protocol
interface	I-Protocol
controllers	I-Protocol
(	O
NICs	O
)	O
.	O
</s>
<s>
Another	O
paper	O
claims	O
no	O
performance	O
improvements	O
when	O
hyper-threading	B-Operating_System
is	O
used	O
for	O
interrupt	O
handling	O
.	O
</s>
<s>
When	O
the	O
first	O
HT	O
processors	B-General_Concept
were	O
released	O
,	O
many	O
operating	B-General_Concept
systems	I-General_Concept
were	O
not	O
optimized	O
for	O
hyper-threading	B-Operating_System
technology	I-Operating_System
(	O
e.g.	O
</s>
<s>
In	O
2006	O
,	O
hyper-threading	B-Operating_System
was	O
criticised	O
for	O
energy	O
inefficiency	O
.	O
</s>
<s>
For	O
example	O
,	O
specialist	O
low-power	O
CPU	O
design	O
company	O
ARM	O
stated	O
that	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
can	O
use	O
up	O
to	O
46%	O
more	O
power	O
than	O
ordinary	O
dual-core	B-Architecture
designs	O
.	O
</s>
<s>
Furthermore	O
,	O
they	O
claimed	O
that	O
SMT	O
increases	O
cache	B-General_Concept
thrashing	I-General_Concept
by	O
42%	O
,	O
whereas	O
dual	B-Architecture
core	I-Architecture
results	O
in	O
a	O
37%	O
decrease	O
.	O
</s>
<s>
In	O
2010	O
,	O
ARM	O
said	O
it	O
might	O
include	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
in	O
its	O
future	O
chips	O
;	O
however	O
,	O
this	O
was	O
rejected	O
in	O
favor	O
of	O
their	O
2012	O
64-bit	O
design	O
.	O
</s>
<s>
In	O
2013	O
,	O
Intel	O
dropped	O
SMT	O
in	O
favor	O
of	O
out-of-order	B-General_Concept
execution	I-General_Concept
for	O
its	O
Silvermont	B-Device
processor	O
cores	O
,	O
as	O
they	O
found	O
this	O
gave	O
better	O
performance	O
with	O
better	O
power	O
efficiency	O
than	O
a	O
lower	O
number	O
of	O
cores	O
with	O
SMT	O
.	O
</s>
<s>
In	O
2017	O
,	O
it	O
was	O
revealed	O
Intel	O
's	O
Skylake	O
and	O
Kaby	O
Lake	O
processors	B-General_Concept
had	O
a	O
bug	O
with	O
their	O
implementation	O
of	O
hyper-threading	B-Operating_System
that	O
could	O
cause	O
data	O
loss	O
.	O
</s>
<s>
Microcode	B-Device
updates	O
were	O
later	O
released	O
to	O
address	O
the	O
issue	O
.	O
</s>
<s>
In	O
2019	O
,	O
with	O
Coffee	B-Device
Lake	I-Device
,	O
Intel	O
temporarily	O
moved	O
away	O
from	O
including	O
hyper-threading	B-Operating_System
in	O
mainstream	O
Core	O
i7	O
desktop	O
processors	B-General_Concept
except	O
for	O
highest-end	O
Core	O
i9	O
parts	O
or	O
Pentium	O
Gold	O
CPUs	O
.	O
</s>
<s>
It	O
also	O
started	O
recommending	O
disabling	O
hyper-threading	B-Operating_System
as	O
new	B-Error_Name
CPU	I-Error_Name
vulnerability	I-Error_Name
attacks	O
were	O
revealed	O
which	O
could	O
be	O
mitigated	O
by	O
disabling	O
HT	O
.	O
</s>
<s>
Potential	O
solutions	O
to	O
this	O
include	O
the	O
processor	O
changing	O
its	O
cache	O
eviction	O
strategy	O
or	O
the	O
operating	B-General_Concept
system	I-General_Concept
preventing	O
the	O
simultaneous	O
execution	O
,	O
on	O
the	O
same	O
physical	O
core	O
,	O
of	O
threads	O
with	O
different	O
privileges	O
.	O
</s>
<s>
In	O
2018	O
the	O
OpenBSD	B-Operating_System
operating	B-General_Concept
system	I-General_Concept
has	O
disabled	O
hyper-threading	B-Operating_System
"	O
in	O
order	O
to	O
avoid	O
data	O
potentially	O
leaking	O
from	O
applications	O
to	O
other	O
software	O
"	O
caused	O
by	O
the	O
Foreshadow/L1TF	B-Device
vulnerabilities	O
.	O
</s>
<s>
In	O
2019	O
a	O
set	B-Device
of	I-Device
vulnerabilities	I-Device
led	O
to	O
security	O
experts	O
recommending	O
the	O
disabling	O
of	O
hyper-threading	B-Operating_System
on	O
all	O
devices	O
.	O
</s>
