<s>
Hybrid	B-General_Concept
Memory	I-General_Concept
Cube	I-General_Concept
(	O
HMC	O
)	O
is	O
a	O
high-performance	O
computer	O
random-access	B-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
)	O
interface	O
for	O
through-silicon	B-Algorithm
vias	I-Algorithm
(	O
TSV	O
)	O
-based	O
stacked	O
DRAM	O
memory	O
competing	O
with	O
the	O
incompatible	O
rival	O
interface	O
High	O
Bandwidth	O
Memory	O
(	O
HBM	O
)	O
.	O
</s>
<s>
Hybrid	B-General_Concept
Memory	I-General_Concept
Cube	I-General_Concept
was	O
co-developed	O
by	O
Samsung	B-Application
Electronics	O
and	O
Micron	O
Technology	O
in	O
2011	O
,	O
and	O
announced	O
by	O
Micron	O
in	O
September	O
2011	O
.	O
</s>
<s>
The	B-General_Concept
Hybrid	I-General_Concept
Memory	I-General_Concept
Cube	I-General_Concept
Consortium	I-General_Concept
(	O
HMCC	O
)	O
is	O
backed	O
by	O
several	O
major	O
technology	O
companies	O
including	O
Samsung	B-Application
,	O
Micron	O
Technology	O
,	O
Open-Silicon	O
,	O
ARM	O
,	O
HP	O
(	O
since	O
withdrawn	O
)	O
,	O
Microsoft	O
(	O
since	O
withdrawn	O
)	O
,	O
Altera	O
(	O
acquired	O
by	O
Intel	O
in	O
late	O
2015	O
)	O
,	O
and	O
Xilinx	O
.	O
</s>
<s>
HMC	O
combines	O
through-silicon	B-Algorithm
vias	I-Algorithm
(	O
TSV	O
)	O
and	O
microbumps	B-Algorithm
to	O
connect	O
multiple	O
(	O
currently	O
4	O
to	O
8	O
)	O
dies	O
of	O
memory	O
cell	O
arrays	O
on	O
top	O
of	O
each	O
other	O
.	O
</s>
