<s>
Hybrid-core	B-Architecture
computing	I-Architecture
is	O
the	O
technique	O
of	O
extending	O
a	O
commodity	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
e.g.	O
</s>
<s>
x86	B-Operating_System
)	O
with	O
application-specific	O
instructions	O
to	O
accelerate	O
application	O
performance	O
.	O
</s>
<s>
Hybrid-core	O
processing	O
differs	O
from	O
general	O
heterogeneous	O
computing	O
in	O
that	O
the	O
computational	O
units	O
share	O
a	O
common	O
logical	O
address	O
space	O
,	O
and	O
an	O
executable	O
is	O
composed	O
of	O
a	O
single	O
instruction	O
stream	O
—	O
in	O
essence	O
a	O
contemporary	O
coprocessor	B-General_Concept
.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
of	O
a	O
hybrid-core	B-Architecture
computing	I-Architecture
system	O
contains	O
instructions	O
that	O
can	O
be	O
dispatched	O
either	O
to	O
the	O
host	O
instruction	B-General_Concept
set	I-General_Concept
or	O
to	O
the	O
application-specific	O
hardware	O
.	O
</s>
<s>
Typically	O
,	O
hybrid-core	B-Architecture
computing	I-Architecture
is	O
best	O
deployed	O
where	O
the	O
predominance	O
of	O
computational	O
cycles	O
are	O
spent	O
in	O
a	O
few	O
identifiable	O
kernels	O
,	O
as	O
is	O
often	O
seen	O
in	O
high-performance	B-Architecture
computing	I-Architecture
applications	O
.	O
</s>
<s>
Hybrid-core	B-Architecture
computing	I-Architecture
is	O
used	O
to	O
accelerate	O
applications	O
beyond	O
what	O
is	O
currently	O
physically	O
possible	O
with	O
off-the-shelf	O
processors	O
,	O
or	O
to	O
lower	O
power	O
&	O
cooling	O
costs	O
in	O
a	O
data	O
center	O
by	O
reducing	O
computational	O
footprint	O
.	O
</s>
