<s>
High-level	B-General_Concept
synthesis	I-General_Concept
(	O
HLS	O
)	O
,	O
sometimes	O
referred	O
to	O
as	O
C	B-General_Concept
synthesis	I-General_Concept
,	O
electronic	O
system-level	O
(	O
ESL	O
)	O
synthesis	O
,	O
algorithmic	B-General_Concept
synthesis	I-General_Concept
,	O
or	O
behavioral	B-General_Concept
synthesis	I-General_Concept
,	O
is	O
an	O
automated	O
design	O
process	O
that	O
takes	O
an	O
abstract	O
behavioral	O
specification	O
of	O
a	O
digital	O
system	O
and	O
finds	O
a	O
register-transfer	O
level	O
structure	O
that	O
realizes	O
the	O
given	O
behavior	O
.	O
</s>
<s>
Early	O
HLS	O
explored	O
a	O
variety	O
of	O
input	O
specification	O
languages	O
,	O
although	O
recent	O
research	O
and	O
commercial	O
applications	O
generally	O
accept	O
synthesizable	O
subsets	O
of	O
ANSI	O
C/C	O
++	O
/SystemC/MATLAB	O
.	O
</s>
<s>
The	O
code	O
is	O
analyzed	O
,	O
architecturally	O
constrained	O
,	O
and	O
scheduled	O
to	O
transcompile	B-Language
into	O
a	O
register-transfer	O
level	O
(	O
RTL	O
)	O
design	O
in	O
a	O
hardware	O
description	O
language	O
(	O
HDL	O
)	O
,	O
which	O
is	O
in	O
turn	O
commonly	O
synthesized	O
to	O
the	O
gate	O
level	O
by	O
the	O
use	O
of	O
a	O
logic	O
synthesis	O
tool	O
.	O
</s>
<s>
While	O
logic	O
synthesis	O
uses	O
an	O
RTL	O
description	O
of	O
the	O
design	O
,	O
high-level	B-General_Concept
synthesis	I-General_Concept
works	O
at	O
a	O
higher	O
level	O
of	O
abstraction	O
,	O
starting	O
with	O
an	O
algorithmic	O
description	O
in	O
a	O
high-level	O
language	O
such	O
as	O
SystemC	B-Language
and	O
ANSI	O
C/C	O
++	O
.	O
</s>
<s>
The	O
high-level	B-General_Concept
synthesis	I-General_Concept
tools	O
handle	O
the	O
micro-architecture	O
and	O
transform	O
untimed	O
or	O
partially	O
timed	O
functional	O
code	O
into	O
fully	O
timed	O
RTL	O
implementations	O
,	O
automatically	O
creating	O
cycle-by-cycle	O
detail	O
for	O
hardware	O
implementation	O
.	O
</s>
<s>
Scheduling	O
partitions	O
the	O
algorithm	O
in	O
control	O
steps	O
that	O
are	O
used	O
to	O
define	O
the	O
states	O
in	O
the	O
finite-state	B-Architecture
machine	I-Architecture
.	O
</s>
<s>
First	O
generation	O
behavioral	B-General_Concept
synthesis	I-General_Concept
was	O
introduced	O
by	O
Synopsys	O
in	O
1994	O
as	O
Behavioral	O
Compiler	O
and	O
used	O
Verilog	B-Language
or	O
VHDL	B-Language
as	O
input	O
languages	O
.	O
</s>
<s>
Tools	O
based	O
on	O
behavioral	O
Verilog	B-Language
or	O
VHDL	B-Language
were	O
not	O
widely	O
adopted	O
in	O
part	O
because	O
neither	O
languages	O
nor	O
the	O
partially	O
timed	O
abstraction	O
were	O
well	O
suited	O
to	O
modeling	O
behavior	O
at	O
a	O
high	O
level	O
.	O
</s>
<s>
In	O
1998	O
,	O
Forte	O
Design	O
Systems	O
introduced	O
its	O
Cynthesizer	O
tool	O
which	O
used	O
SystemC	B-Language
as	O
an	O
entry	O
language	O
instead	O
of	O
Verilog	B-Language
or	O
VHDL	B-Language
.	O
</s>
<s>
Cynthesizer	O
was	O
adopted	O
by	O
many	O
Japanese	O
companies	O
in	O
2000	O
as	O
Japan	O
had	O
a	O
very	O
mature	O
SystemC	B-Language
user	O
community	O
.	O
</s>
<s>
The	O
first	O
high-level	B-General_Concept
synthesis	I-General_Concept
tapeout	O
was	O
achieved	O
in	O
2001	O
by	O
Sony	O
using	O
Cynthesizer	O
.	O
</s>
<s>
The	O
most	O
common	O
source	O
inputs	O
for	O
high-level	B-General_Concept
synthesis	I-General_Concept
are	O
based	O
on	O
standard	O
languages	O
such	O
as	O
ANSI	O
C/C	O
++	O
,	O
SystemC	B-Language
and	O
MATLAB	B-Language
.	O
</s>
<s>
High-level	B-General_Concept
synthesis	I-General_Concept
typically	O
also	O
includes	O
a	O
bit-accurate	O
executable	O
specification	O
as	O
input	O
,	O
since	O
to	O
derive	O
an	O
efficient	O
hardware	O
implementation	O
,	O
additional	O
information	O
is	O
needed	O
on	O
what	O
is	O
an	O
acceptable	O
Mean-Square	O
Error	O
or	O
Bit-Error	O
Rate	O
etc	O
.	O
</s>
<s>
This	O
bit-accurate	O
specification	O
makes	O
the	O
high	B-General_Concept
level	I-General_Concept
synthesis	I-General_Concept
source	O
specification	O
functionally	O
complete	O
.	O
</s>
<s>
Normally	O
the	O
tools	O
infer	O
from	O
the	O
high	O
level	O
code	O
a	O
Finite	B-Architecture
State	I-Architecture
Machine	I-Architecture
and	O
a	O
Datapath	O
that	O
implement	O
arithmetic	O
operations	O
.	O
</s>
<s>
The	O
high-level	B-General_Concept
synthesis	I-General_Concept
process	O
consists	O
of	O
a	O
number	O
of	O
activities	O
.	O
</s>
<s>
Various	O
high-level	B-General_Concept
synthesis	I-General_Concept
tools	O
perform	O
these	O
activities	O
in	O
different	O
orders	O
using	O
different	O
algorithms	O
.	O
</s>
<s>
Some	O
high-level	B-General_Concept
synthesis	I-General_Concept
tools	O
combine	O
some	O
of	O
these	O
activities	O
or	O
perform	O
them	O
iteratively	O
to	O
converge	O
on	O
the	O
desired	O
solution	O
.	O
</s>
<s>
Interface	O
Synthesis	O
refers	O
to	O
the	O
ability	O
to	O
accept	O
pure	O
C/C	O
++	O
description	O
as	O
its	O
input	O
,	O
then	O
use	O
automated	O
interface	O
synthesis	O
technology	O
to	O
control	O
the	O
timing	O
and	O
communications	O
protocol	O
on	O
the	O
design	O
interface	O
.	O
</s>
<s>
Status	O
Compiler	O
Owner	O
License	O
Input	O
Output	O
Year	O
Domain	O
TestBench	O
FP	O
FixP	O
In	O
UseStratus	O
HLSCadence	O
Design	O
SystemsCommercialC/C	O
++	O
SystemCRTL2015AllYesYesYesAUGHTIMA	O
Lab.AcademicC	O
subsetVHDL2012AllYesNoNoeXCiteY	O
ExplorationsCommercialCVHDL/Verilog2001AllYesNoYesBambuPoliMiAcademicCVHDL/Verilog2012AllYesYesNoBluespecBlueSpec	O
Inc.BSD-3BSVSystemVerilog2007AllNoNoNoQCCCacheQ	O
Systems	O
,	O
Inc.CommercialC/C	O
++	O
/FortanHost	O
Executable	O
+	O
FPGA	O
Bit	O
file	O
(	O
SystemVerilog	B-Language
is	O
intermediate	O
)	O
2018All	O
-	O
multi-core	O
and	O
heterogeneous	O
computeYes	O
(	O
C++	B-Language
)	O
YesYesCHCAltiumCommercialC	O
subsetVHDL/Verilog2008AllNoYesYesCoDeveloperImpulse	O
AcceleratedCommercialImpulse-CVHDL2003ImageStreamingYesYesNoHDL	O
CoderMathWorksCommercialMATLAB	O
,	O
Simulink	O
,	O
Stateflow	O
,	O
SimscapeVHDL	O
/	O
Verilog2003Control	O
Systems	O
,	O
Signal	O
Processing	O
,	O
Wireless	O
,	O
Radar	O
,	O
Communications	O
,	O
Image	O
and	O
Computer	O
VisionYesYesYesCyberWorkbenchNECCommercialBDL	O
,	O
SystemCVHDL/Verilog2011AllCycle/FormalYesYesCatapultMentor	O
( Siemens	O
business	O
)	O
CommercialC	O
,	O
C++	B-Language
,	O
SystemC	B-Language
VHDL/Verilog2004AllYesYesYesDWARVTU	O
.	O
</s>
<s>
BretagneAcademicC/C	O
++VHDL2010DSPYesNoYesHastlayerLombiq	O
TechnologiesBSD-3C	O
#	O
/C	O
++	O
/F	O
#	O
...	O
(	O
.NET	B-Application
)	O
VHDL2015.NETYesYesYesInstant	O
SoCFPGA	O
CoresCommercialC/C	O
++	O
VHDL/Verilog2019AllYesNoNoIntel	O
High	B-General_Concept
Level	I-General_Concept
Synthesis	I-General_Concept
CompilerIntel	O
FPGA	O
(	O
Formerly	O
Altera	O
)	O
CommercialC/C	O
++Verilog2017AllYesYesYesLegUp	O
HLSLegUp	O
ComputingCommercialC/C	O
++Verilog2015AllYesYesYesLegUpU	O
.	O
</s>
<s>
TorontoAcademicCVerilog2010AllYesYesNoMaxCompilerMaxelerCommercialMaxJRTL2010DataFlowNoYesNoROCCCJacquard	O
Comp.CommercialC	O
subsetVHDL2010StreamingNoYesNoSymphony	O
CSynopsysCommercialC/C	O
++	O
VHDL/Verilog/SystemC2010AllYesNoYesVivadoHLS	O
( formerly	O
AutoPilotfrom	O
AutoESL	O
)	O
XilinxCommercialC/C	O
++	O
/SystemCVHDL/Verilog/SystemC2013AllYesYesYesKiwiU	O
.	O
</s>
