<s>
The	O
Hewlett-Packard	B-Device
Nanoprocessor	I-Device
from	O
HP	O
(	O
part	O
number	O
1820-1692	O
)	O
was	O
a	O
small	O
Control-Oriented	O
Processor	O
microcontroller	B-Architecture
without	O
an	O
ALU	B-General_Concept
nor	O
the	O
ability	O
to	O
add	O
or	O
subtract	O
.	O
</s>
<s>
The	O
Nanoprocessor	B-Device
is	O
an	O
8-bit	O
control-oriented	O
CPU	O
built	O
from	O
nMOS	B-Algorithm
logic	I-Algorithm
.	O
</s>
<s>
The	O
processor	O
has	O
sixteen	O
8-bit	O
registers	B-General_Concept
and	O
an	O
8-bit	O
accumulator	O
.	O
</s>
<s>
A	O
1-bit	O
Extend	O
register	O
(	O
E	O
)	O
acts	O
as	O
a	O
carry	B-Algorithm
flag	I-Algorithm
.	O
</s>
<s>
As	O
well	O
as	O
the	O
11-bit	O
program	B-General_Concept
counter	I-General_Concept
(	O
PC	O
)	O
,	O
it	O
has	O
an	O
11-bit	O
subroutine	B-General_Concept
return	I-General_Concept
register	I-General_Concept
(	O
SRR	O
)	O
and	O
11-bit	O
Interrupt	O
Return	O
Register	O
(	O
IRR	O
)	O
,	O
each	O
acting	O
as	O
a	O
single-level	O
stack	O
.	O
</s>
<s>
In	O
place	O
of	O
an	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
,	O
it	O
has	O
a	O
Control	O
Logic	O
Unit	O
(	O
CLU	O
)	O
and	O
a	O
magnitude	O
comparator	O
.	O
</s>
<s>
For	O
input/output	B-General_Concept
,	O
the	O
Nanoprocessor	B-Device
has	O
7	O
bidirectional	B-Architecture
control	I-Architecture
lines	I-Architecture
as	O
well	O
as	O
15	O
input	O
and	O
15	O
output	O
ports	O
for	O
8-bit	O
data	O
transfers	O
.	O
</s>
<s>
Code	O
for	O
the	O
Nanoprocessor	B-Device
was	O
written	O
in	O
assembly	B-Language
language	I-Language
using	O
an	O
assembler	B-Language
and	O
loader	B-Operating_System
that	O
ran	O
on	O
an	O
HP	B-Device
2100	I-Device
computer	O
.	O
</s>
