<s>
In	O
the	O
domain	O
of	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
design	B-General_Concept
,	O
hazards	B-General_Concept
are	O
problems	O
with	O
the	O
instruction	B-General_Concept
pipeline	I-General_Concept
in	O
CPU	B-General_Concept
microarchitectures	I-General_Concept
when	O
the	O
next	O
instruction	O
cannot	O
execute	O
in	O
the	O
following	O
clock	O
cycle	O
,	O
and	O
can	O
potentially	O
lead	O
to	O
incorrect	O
computation	O
results	O
.	O
</s>
<s>
Three	O
common	O
types	O
of	O
hazards	B-General_Concept
are	O
data	O
hazards	B-General_Concept
,	O
structural	O
hazards	B-General_Concept
,	O
and	O
control	B-General_Concept
hazards	I-General_Concept
(	O
branching	O
hazards	B-General_Concept
)	O
.	O
</s>
<s>
There	O
are	O
several	O
methods	O
used	O
to	O
deal	O
with	O
hazards	B-General_Concept
,	O
including	O
pipeline	O
stalls/pipeline	O
bubbling	O
,	O
operand	B-General_Concept
forwarding	I-General_Concept
,	O
and	O
in	O
the	O
case	O
of	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
the	O
scoreboarding	B-General_Concept
method	O
and	O
the	O
Tomasulo	B-General_Concept
algorithm	I-General_Concept
.	O
</s>
<s>
Instructions	O
in	O
a	O
pipelined	B-General_Concept
processor	I-General_Concept
are	O
performed	O
in	O
several	O
stages	O
,	O
so	O
that	O
at	O
any	O
given	O
time	O
several	O
instructions	O
are	O
being	O
processed	O
in	O
the	O
various	O
stages	O
of	O
the	O
pipeline	B-General_Concept
,	O
such	O
as	O
fetch	O
and	O
execute	O
.	O
</s>
<s>
There	O
are	O
many	O
different	O
instruction	B-General_Concept
pipeline	I-General_Concept
microarchitectures	B-General_Concept
,	O
and	O
instructions	O
may	O
be	O
executed	B-General_Concept
out-of-order	I-General_Concept
.	O
</s>
<s>
A	O
hazard	B-General_Concept
occurs	O
when	O
two	O
or	O
more	O
of	O
these	O
simultaneous	O
(	O
possibly	O
out	O
of	O
order	O
)	O
instructions	O
conflict	O
.	O
</s>
<s>
Data	O
hazards	B-General_Concept
occur	O
when	O
instructions	O
that	O
exhibit	O
data	B-Operating_System
dependence	I-Operating_System
modify	O
data	O
in	O
different	O
stages	O
of	O
a	O
pipeline	B-General_Concept
.	O
</s>
<s>
Ignoring	O
potential	O
data	O
hazards	B-General_Concept
can	O
result	O
in	O
race	B-Operating_System
conditions	I-Operating_System
(	O
also	O
termed	O
race	B-Operating_System
hazards	I-Operating_System
)	O
.	O
</s>
<s>
There	O
are	O
three	O
situations	O
in	O
which	O
a	O
data	O
hazard	B-General_Concept
can	O
occur	O
:	O
</s>
<s>
Read	O
after	O
read	O
(	O
RAR	O
)	O
is	O
not	O
a	O
hazard	B-General_Concept
case	O
.	O
</s>
<s>
A	O
read	O
after	O
write	O
(	O
RAW	O
)	O
data	O
hazard	B-General_Concept
refers	O
to	O
a	O
situation	O
where	O
an	O
instruction	O
refers	O
to	O
a	O
result	O
that	O
has	O
not	O
yet	O
been	O
calculated	O
or	O
retrieved	O
.	O
</s>
<s>
This	O
can	O
occur	O
because	O
even	O
though	O
an	O
instruction	O
is	O
executed	O
after	O
a	O
prior	O
instruction	O
,	O
the	O
prior	O
instruction	O
has	O
been	O
processed	O
only	O
partly	O
through	O
the	O
pipeline	B-General_Concept
.	O
</s>
<s>
However	O
,	O
in	O
a	O
pipeline	B-General_Concept
,	O
when	O
operands	O
are	O
fetched	O
for	O
the	O
2nd	O
operation	O
,	O
the	O
results	O
from	O
the	O
first	O
have	O
not	O
yet	O
been	O
saved	O
,	O
and	O
hence	O
a	O
data	B-Operating_System
dependency	I-Operating_System
occurs	O
.	O
</s>
<s>
A	O
data	B-Operating_System
dependency	I-Operating_System
occurs	O
with	O
instruction	O
,	O
as	O
it	O
is	O
dependent	O
on	O
the	O
completion	O
of	O
instruction	O
.	O
</s>
<s>
A	O
write	O
after	O
read	O
(	O
WAR	O
)	O
data	O
hazard	B-General_Concept
represents	O
a	O
problem	O
with	O
concurrent	B-Architecture
execution	I-Architecture
.	O
</s>
<s>
In	O
any	O
situation	O
with	O
a	O
chance	O
that	O
may	O
finish	O
before	O
(	O
i.e.	O
,	O
with	O
concurrent	B-Architecture
execution	I-Architecture
)	O
,	O
it	O
must	O
be	O
ensured	O
that	O
the	O
result	O
of	O
register	O
is	O
not	O
stored	O
before	O
has	O
had	O
a	O
chance	O
to	O
fetch	O
the	O
operands	O
.	O
</s>
<s>
A	O
write	O
after	O
write	O
(	O
WAW	O
)	O
data	O
hazard	B-General_Concept
may	O
occur	O
in	O
a	O
concurrent	B-Architecture
execution	I-Architecture
environment	O
.	O
</s>
<s>
A	O
structural	O
hazard	B-General_Concept
occurs	O
when	O
two	O
(	O
or	O
more	O
)	O
instructions	O
that	O
are	O
already	O
in	O
pipeline	B-General_Concept
need	O
the	O
same	O
resource	O
.	O
</s>
<s>
The	O
result	O
is	O
that	O
instruction	O
must	O
be	O
executed	O
in	O
series	O
rather	O
than	O
parallel	O
for	O
a	O
portion	O
of	O
pipeline	B-General_Concept
.	O
</s>
<s>
Structural	O
hazards	B-General_Concept
are	O
sometime	O
referred	O
to	O
as	O
resource	O
hazards	B-General_Concept
.	O
</s>
<s>
One	O
solution	O
to	O
such	O
resource	O
hazard	B-General_Concept
is	O
to	O
increase	O
available	O
resources	O
,	O
such	O
as	O
having	O
multiple	O
ports	O
into	O
main	O
memory	O
and	O
multiple	O
ALU	O
(	O
Arithmetic	O
Logic	O
Unit	O
)	O
units	O
.	O
</s>
<s>
Control	O
hazard	B-General_Concept
occurs	O
when	O
the	O
pipeline	B-General_Concept
makes	O
wrong	O
decisions	O
on	O
branch	B-General_Concept
prediction	I-General_Concept
and	O
therefore	O
brings	O
instructions	O
into	O
the	O
pipeline	B-General_Concept
that	O
must	O
subsequently	O
be	O
discarded	O
.	O
</s>
<s>
The	O
term	O
branch	B-General_Concept
hazard	I-General_Concept
also	O
refers	O
to	O
a	O
control	O
hazard	B-General_Concept
.	O
</s>
<s>
Bubbling	B-General_Concept
the	I-General_Concept
pipeline	I-General_Concept
,	O
also	O
termed	O
a	O
pipeline	B-General_Concept
break	I-General_Concept
or	O
pipeline	B-General_Concept
stall	I-General_Concept
,	O
is	O
a	O
method	O
to	O
preclude	O
data	O
,	O
structural	O
,	O
and	O
branch	B-General_Concept
hazards	I-General_Concept
.	O
</s>
<s>
As	O
instructions	O
are	O
fetched	O
,	O
control	O
logic	O
determines	O
whether	O
a	O
hazard	B-General_Concept
could/will	O
occur	O
.	O
</s>
<s>
If	O
this	O
is	O
true	O
,	O
then	O
the	O
control	O
logic	O
inserts	O
s	O
(	O
s	O
)	O
into	O
the	O
pipeline	B-General_Concept
.	O
</s>
<s>
Thus	O
,	O
before	O
the	O
next	O
instruction	O
(	O
which	O
would	O
cause	O
the	O
hazard	B-General_Concept
)	O
executes	O
,	O
the	O
prior	O
one	O
will	O
have	O
had	O
sufficient	O
time	O
to	O
finish	O
and	O
prevent	O
the	O
hazard	B-General_Concept
.	O
</s>
<s>
If	O
the	O
number	O
of	O
s	O
equals	O
the	O
number	O
of	O
stages	O
in	O
the	O
pipeline	B-General_Concept
,	O
the	O
processor	O
has	O
been	O
cleared	O
of	O
all	O
instructions	O
and	O
can	O
proceed	O
free	O
from	O
hazards	B-General_Concept
.	O
</s>
<s>
Flushing	O
the	O
pipeline	B-General_Concept
occurs	O
when	O
a	O
branch	O
instruction	O
jumps	O
to	O
a	O
new	O
memory	O
location	O
,	O
invalidating	O
all	O
prior	O
stages	O
in	O
the	O
pipeline	B-General_Concept
.	O
</s>
<s>
These	O
prior	O
stages	O
are	O
cleared	O
,	O
allowing	O
the	O
pipeline	B-General_Concept
to	O
continue	O
at	O
the	O
new	O
instruction	O
indicated	O
by	O
the	O
branch	O
.	O
</s>
<s>
There	O
are	O
several	O
main	O
solutions	O
and	O
algorithms	O
used	O
to	O
resolve	O
data	O
hazards	B-General_Concept
:	O
</s>
<s>
In	O
the	O
case	O
of	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
the	O
algorithm	O
used	O
can	O
be	O
:	O
</s>
<s>
The	O
task	O
of	O
removing	O
data	B-Operating_System
dependencies	I-Operating_System
can	O
be	O
delegated	O
to	O
the	O
compiler	O
,	O
which	O
can	O
fill	O
in	O
an	O
appropriate	O
number	O
of	O
instructions	O
between	O
dependent	O
instructions	O
to	O
ensure	O
correct	O
operation	O
,	O
or	O
re-order	O
instructions	O
where	O
possible	O
.	O
</s>
<s>
However	O
,	O
if	O
i1	O
(	O
write	O
3	O
to	O
register	O
1	O
)	O
does	O
not	O
fully	O
exit	O
the	O
pipeline	B-General_Concept
before	O
i2	O
starts	O
executing	O
,	O
it	O
means	O
that	O
R1	O
does	O
not	O
contain	O
the	O
value	O
3	O
when	O
i2	O
performs	O
its	O
addition	O
.	O
</s>
<s>
With	O
forwarding	O
enabled	O
,	O
the	O
Instruction	O
Decode/Execution	O
(	O
ID/EX	O
)	O
stage	O
of	O
the	O
pipeline	B-General_Concept
now	O
has	O
two	O
inputs	O
:	O
the	O
value	O
read	O
from	O
the	O
register	O
specified	O
(	O
in	O
this	O
example	O
,	O
the	O
value	O
6	O
from	O
Register	O
1	O
)	O
,	O
and	O
the	O
new	O
value	O
of	O
Register	O
1	O
(	O
in	O
this	O
example	O
,	O
this	O
value	O
is	O
3	O
)	O
which	O
is	O
sent	O
from	O
the	O
next	O
stage	O
Instruction	O
Execute/Memory	O
Access	O
(	O
EX/MEM	O
)	O
.	O
</s>
<s>
To	O
avoid	O
control	B-General_Concept
hazards	I-General_Concept
microarchitectures	B-General_Concept
can	O
:	O
</s>
<s>
In	O
the	O
event	O
that	O
a	O
branch	O
causes	O
a	O
pipeline	B-General_Concept
bubble	I-General_Concept
after	O
incorrect	O
instructions	O
have	O
entered	O
the	O
pipeline	B-General_Concept
,	O
care	O
must	O
be	O
taken	O
to	O
prevent	O
any	O
of	O
the	O
wrongly-loaded	O
instructions	O
from	O
having	O
any	O
effect	O
on	O
the	O
processor	O
state	O
excluding	O
energy	O
wasted	O
processing	O
them	O
before	O
they	O
were	O
discovered	O
to	O
be	O
loaded	O
incorrectly	O
.	O
</s>
