<s>
The	O
Harvard	B-Architecture
architecture	I-Architecture
is	O
a	O
computer	B-General_Concept
architecture	I-General_Concept
with	O
separate	O
storage	B-General_Concept
and	O
signal	O
pathways	O
for	O
instructions	B-Language
and	O
data	O
.	O
</s>
<s>
It	O
contrasts	O
with	O
the	O
von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
,	O
where	O
program	O
instructions	B-Language
and	O
data	O
share	O
the	O
same	O
memory	O
and	O
pathways	O
.	O
</s>
<s>
The	O
term	O
originated	O
from	O
the	O
Harvard	B-Device
Mark	I-Device
I	I-Device
relay-based	O
computer	O
,	O
which	O
stored	O
instructions	B-Language
on	O
punched	O
tape	O
(	O
24	O
bits	O
wide	O
)	O
and	O
data	O
in	O
electro-mechanical	O
counters	O
(	O
although	O
both	O
the	O
origin	O
,	O
and	O
the	O
meaning	O
commonly	O
given	O
the	O
term	O
'	O
Harvard	B-Architecture
architecture	I-Architecture
 '	O
,	O
has	O
been	O
challenged	O
in	O
'	O
The	O
Myth	O
of	O
the	O
Harvard	B-Architecture
Architecture	I-Architecture
 '	O
published	O
by	O
the	O
IEEE	O
Annals	O
of	O
the	O
History	O
of	O
Computing	O
)	O
.	O
</s>
<s>
These	O
early	O
machines	O
had	O
data	O
storage	B-General_Concept
entirely	O
contained	O
within	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
,	O
and	O
provided	O
no	O
access	O
to	O
the	O
instruction	O
storage	B-General_Concept
as	O
data	O
.	O
</s>
<s>
Programs	O
needed	O
to	O
be	O
loaded	O
by	O
an	O
operator	O
;	O
the	O
processor	O
could	O
not	O
initialize	B-Operating_System
itself	O
.	O
</s>
<s>
Modern	O
processors	O
appear	O
to	O
the	O
user	O
to	O
be	O
systems	O
with	O
von	B-Architecture
Neumann	I-Architecture
architectures	I-Architecture
,	O
with	O
the	O
program	O
code	O
stored	O
in	O
the	O
same	O
main	O
memory	O
as	O
the	O
data	O
.	O
</s>
<s>
For	O
performance	O
reasons	O
,	O
internally	O
and	O
largely	O
invisible	O
to	O
the	O
user	O
,	O
most	O
designs	O
have	O
separate	O
processor	B-General_Concept
caches	I-General_Concept
for	O
the	O
instructions	B-Language
and	O
data	O
,	O
with	O
separate	O
pathways	O
into	O
the	O
processor	O
for	O
each	O
.	O
</s>
<s>
This	O
is	O
one	O
form	O
of	O
what	O
is	O
known	O
as	O
the	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
.	O
</s>
<s>
Harvard	B-Architecture
architecture	I-Architecture
is	O
historically	O
,	O
and	O
traditionally	O
,	O
split	O
into	O
two	O
address	O
spaces	O
,	O
but	O
having	O
three	O
,	O
i.e.	O
</s>
<s>
In	O
a	O
Harvard	B-Architecture
architecture	I-Architecture
,	O
there	O
is	O
no	O
need	O
to	O
make	O
the	O
two	O
memories	O
share	O
characteristics	O
.	O
</s>
<s>
In	O
particular	O
,	O
the	O
word	O
width	O
,	O
timing	O
,	O
implementation	O
technology	O
,	O
and	O
memory	B-General_Concept
address	I-General_Concept
structure	O
can	O
differ	O
.	O
</s>
<s>
In	O
some	O
systems	O
,	O
instructions	B-Language
for	O
pre-programmed	O
tasks	O
can	O
be	O
stored	O
in	O
read-only	B-Device
memory	I-Device
while	O
data	O
memory	O
generally	O
requires	O
read-write	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
In	O
a	O
system	O
with	O
a	O
pure	O
von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
,	O
instructions	B-Language
and	O
data	O
are	O
stored	O
in	O
the	O
same	O
memory	O
,	O
so	O
instructions	B-Language
are	O
fetched	O
over	O
the	O
same	O
data	O
path	O
used	O
to	O
fetch	O
data	O
.	O
</s>
<s>
This	O
means	O
that	O
a	O
CPU	B-General_Concept
cannot	O
simultaneously	O
read	O
an	O
instruction	O
and	O
read	O
or	O
write	O
data	O
from	O
or	O
to	O
the	O
memory	O
.	O
</s>
<s>
In	O
a	O
computer	O
using	O
the	O
Harvard	B-Architecture
architecture	I-Architecture
,	O
the	O
CPU	B-General_Concept
can	O
both	O
read	O
an	O
instruction	O
and	O
perform	O
a	O
data	O
memory	O
access	O
at	O
the	O
same	O
time	O
,	O
even	O
without	O
a	O
cache	B-General_Concept
.	O
</s>
<s>
A	O
Harvard	B-Architecture
architecture	I-Architecture
computer	O
can	O
thus	O
be	O
faster	O
for	O
a	O
given	O
circuit	O
complexity	O
because	O
instruction	O
fetches	O
and	O
data	O
access	O
do	O
not	O
contend	O
for	O
a	O
single	O
memory	O
pathway	O
.	O
</s>
<s>
Also	O
,	O
a	O
Harvard	B-Architecture
architecture	I-Architecture
machine	O
has	O
distinct	O
code	O
and	O
data	O
address	O
spaces	O
:	O
instruction	O
address	O
zero	O
is	O
not	O
the	O
same	O
as	O
data	O
address	O
zero	O
.	O
</s>
<s>
A	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
machine	O
is	O
very	O
much	O
like	O
a	O
Harvard	B-Architecture
architecture	I-Architecture
machine	O
,	O
but	O
it	O
relaxes	O
the	O
strict	O
separation	O
between	O
instruction	O
and	O
data	O
while	O
still	O
letting	O
the	O
CPU	B-General_Concept
concurrently	O
access	O
two	O
(	O
or	O
more	O
)	O
memory	O
buses	O
.	O
</s>
<s>
The	O
most	O
common	O
modification	O
includes	O
separate	O
instruction	O
and	O
data	B-General_Concept
caches	I-General_Concept
backed	O
by	O
a	O
common	O
address	O
space	O
.	O
</s>
<s>
While	O
the	O
CPU	B-General_Concept
executes	O
from	O
cache	B-General_Concept
,	O
it	O
acts	O
as	O
a	O
pure	O
Harvard	O
machine	O
.	O
</s>
<s>
This	O
modification	O
is	O
widespread	O
in	O
modern	O
processors	O
,	O
such	O
as	O
the	O
ARM	B-Architecture
architecture	I-Architecture
,	O
Power	B-Architecture
ISA	I-Architecture
and	O
x86	B-Operating_System
processors	O
.	O
</s>
<s>
It	O
is	O
sometimes	O
loosely	O
called	O
a	O
Harvard	B-Architecture
architecture	I-Architecture
,	O
overlooking	O
the	O
fact	O
that	O
it	O
is	O
actually	O
"	O
modified	O
"	O
.	O
</s>
<s>
Another	O
modification	O
provides	O
a	O
pathway	O
between	O
the	O
instruction	O
memory	O
(	O
such	O
as	O
ROM	B-Device
or	O
flash	B-Device
memory	I-Device
)	O
and	O
the	O
CPU	B-General_Concept
to	O
allow	O
words	O
from	O
the	O
instruction	O
memory	O
to	O
be	O
treated	O
as	O
read-only	O
data	O
.	O
</s>
<s>
This	O
technique	O
is	O
used	O
in	O
some	O
microcontrollers	B-Architecture
,	O
including	O
the	O
Atmel	B-Architecture
AVR	I-Architecture
.	O
</s>
<s>
Special	O
machine	B-Language
language	I-Language
instructions	B-Language
are	O
provided	O
to	O
read	O
data	O
from	O
the	O
instruction	O
memory	O
,	O
or	O
the	O
instruction	O
memory	O
can	O
be	O
accessed	O
using	O
a	O
peripheral	O
interface	O
.	O
</s>
<s>
(	O
This	O
is	O
distinct	O
from	O
instructions	B-Language
which	O
themselves	O
embed	O
constant	O
data	O
,	O
although	O
for	O
individual	O
constants	O
the	O
two	O
mechanisms	O
can	O
substitute	O
for	O
each	O
other	O
.	O
)	O
</s>
<s>
In	O
recent	O
years	O
,	O
the	O
speed	O
of	O
the	O
CPU	B-General_Concept
has	O
grown	O
many	O
times	O
in	O
comparison	O
to	O
the	O
access	O
speed	O
of	O
the	O
main	O
memory	O
.	O
</s>
<s>
If	O
,	O
for	O
instance	O
,	O
every	O
instruction	O
run	O
in	O
the	O
CPU	B-General_Concept
requires	O
an	O
access	O
to	O
memory	O
,	O
the	O
computer	O
gains	O
nothing	O
for	O
increased	O
CPU	B-General_Concept
speed	O
—	O
a	O
problem	O
referred	O
to	O
as	O
being	O
memory	B-General_Concept
bound	I-General_Concept
.	O
</s>
<s>
The	O
solution	O
is	O
to	O
provide	O
a	O
small	O
amount	O
of	O
very	O
fast	O
memory	O
known	O
as	O
a	O
CPU	B-General_Concept
cache	I-General_Concept
which	O
holds	O
recently	O
accessed	O
data	O
.	O
</s>
<s>
As	O
long	O
as	O
the	O
data	O
that	O
the	O
CPU	B-General_Concept
needs	O
is	O
in	O
the	O
cache	B-General_Concept
,	O
the	O
performance	O
is	O
much	O
higher	O
than	O
it	O
is	O
when	O
the	O
CPU	B-General_Concept
has	O
to	O
get	O
the	O
data	O
from	O
the	O
main	O
memory	O
.	O
</s>
<s>
On	O
the	O
other	O
side	O
,	O
however	O
,	O
it	O
may	O
still	O
be	O
limited	O
to	O
storing	O
repetitive	O
programs	O
or	O
data	O
and	O
still	O
has	O
a	O
storage	B-General_Concept
size	O
limitation	O
,	O
and	O
other	O
potential	O
problems	O
associated	O
with	O
it	O
.	O
</s>
<s>
Modern	O
high	O
performance	O
CPU	B-General_Concept
chip	O
designs	O
incorporate	O
aspects	O
of	O
both	O
Harvard	O
and	O
von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
.	O
</s>
<s>
In	O
particular	O
,	O
the	O
"	O
split	O
cache	B-General_Concept
"	O
version	O
of	O
the	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
is	O
very	O
common	O
.	O
</s>
<s>
CPU	B-General_Concept
cache	I-General_Concept
memory	O
is	O
divided	O
into	O
an	O
instruction	O
cache	B-General_Concept
and	O
a	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Harvard	B-Architecture
architecture	I-Architecture
is	O
used	O
as	O
the	O
CPU	B-General_Concept
accesses	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
In	O
the	O
case	O
of	O
a	O
cache	B-General_Concept
miss	O
,	O
however	O
,	O
the	O
data	O
is	O
retrieved	O
from	O
the	O
main	O
memory	O
,	O
which	O
is	O
not	O
formally	O
divided	O
into	O
separate	O
instruction	O
and	O
data	O
sections	O
,	O
although	O
it	O
may	O
well	O
have	O
separate	O
memory	O
controllers	O
used	O
for	O
concurrent	O
access	O
to	O
RAM	B-Architecture
,	O
ROM	B-Device
and	O
(	O
NOR	O
)	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
Thus	O
,	O
while	O
a	O
von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
is	O
visible	O
in	O
some	O
contexts	O
,	O
such	O
as	O
when	O
data	O
and	O
code	O
come	O
through	O
the	O
same	O
memory	O
controller	O
,	O
the	O
hardware	O
implementation	O
gains	O
the	O
efficiencies	O
of	O
the	O
Harvard	B-Architecture
architecture	I-Architecture
for	O
cache	B-General_Concept
accesses	O
and	O
at	O
least	O
some	O
main	O
memory	O
accesses	O
.	O
</s>
<s>
The	O
von	O
Neumann	O
nature	O
of	O
memory	O
is	O
then	O
visible	O
when	O
instructions	B-Language
are	O
written	O
as	O
data	O
by	O
the	O
CPU	B-General_Concept
and	O
software	O
must	O
ensure	O
that	O
the	O
caches	B-General_Concept
(	O
data	O
and	O
instruction	O
)	O
and	O
write	O
buffer	O
are	O
synchronized	O
before	O
trying	O
to	O
execute	O
those	O
just-written	O
instructions	B-Language
.	O
</s>
<s>
The	O
principal	O
advantage	O
of	O
the	O
pure	O
Harvard	B-Architecture
architecture	I-Architecture
—	O
simultaneous	O
access	O
to	O
more	O
than	O
one	O
memory	O
system	O
—	O
has	O
been	O
reduced	O
by	O
modified	O
Harvard	O
processors	O
using	O
modern	O
CPU	B-General_Concept
cache	I-General_Concept
systems	O
.	O
</s>
<s>
Relatively	O
pure	O
Harvard	B-Architecture
architecture	I-Architecture
machines	O
are	O
used	O
mostly	O
in	O
applications	O
where	O
trade-offs	O
,	O
like	O
the	O
cost	O
and	O
power	O
savings	O
from	O
omitting	O
caches	B-General_Concept
,	O
outweigh	O
the	O
programming	O
penalties	O
from	O
featuring	O
distinct	O
code	O
and	O
data	O
address	O
spaces	O
.	O
</s>
<s>
Digital	B-Architecture
signal	I-Architecture
processors	I-Architecture
(	O
DSPs	O
)	O
generally	O
execute	O
small	O
,	O
highly	O
optimized	O
audio	O
or	O
video	O
processing	O
algorithms	O
.	O
</s>
<s>
They	O
avoid	O
caches	B-General_Concept
because	O
their	O
behavior	O
must	O
be	O
extremely	O
reproducible	O
.	O
</s>
<s>
Consequently	O
,	O
some	O
DSPs	O
feature	O
multiple	O
data	O
memories	O
in	O
distinct	O
address	O
spaces	O
to	O
facilitate	O
SIMD	B-Device
and	O
VLIW	B-General_Concept
processing	O
.	O
</s>
<s>
Texas	B-Architecture
Instruments	I-Architecture
TMS320	I-Architecture
C55x	O
processors	O
,	O
for	O
one	O
example	O
,	O
feature	O
multiple	O
parallel	O
data	O
buses	O
(	O
two	O
write	O
,	O
three	O
read	O
)	O
and	O
one	O
instruction	O
bus	O
.	O
</s>
<s>
Microcontrollers	B-Architecture
are	O
characterized	O
by	O
having	O
small	O
amounts	O
of	O
program	O
(	O
flash	B-Device
memory	I-Device
)	O
and	O
data	O
(	O
SRAM	B-Architecture
)	O
memory	O
,	O
and	O
take	O
advantage	O
of	O
the	O
Harvard	B-Architecture
architecture	I-Architecture
to	O
speed	O
processing	O
by	O
concurrent	O
instruction	O
and	O
data	O
access	O
.	O
</s>
<s>
The	O
separate	O
storage	B-General_Concept
means	O
the	O
program	O
and	O
data	O
memories	O
may	O
feature	O
different	O
bit	O
widths	O
,	O
for	O
example	O
using	O
16-bit-wide	O
instructions	B-Language
and	O
8-bit-wide	O
data	O
.	O
</s>
<s>
They	O
also	O
mean	O
that	O
instruction	B-General_Concept
prefetch	I-General_Concept
can	O
be	O
performed	O
in	O
parallel	O
with	O
other	O
activities	O
.	O
</s>
<s>
Examples	O
include	O
the	O
PIC	B-Architecture
by	O
Microchip	O
Technology	O
,	O
Inc	O
.	O
and	O
the	O
AVR	B-Architecture
by	O
Atmel	O
Corp	O
(	O
now	O
part	O
of	O
Microchip	O
Technology	O
)	O
.	O
</s>
<s>
Even	O
in	O
these	O
cases	O
,	O
it	O
is	O
common	O
to	O
employ	O
special	O
instructions	B-Language
in	O
order	O
to	O
access	O
program	B-Device
memory	I-Device
as	O
though	O
it	O
were	O
data	O
for	O
read-only	O
tables	O
,	O
or	O
for	O
reprogramming	O
;	O
those	O
processors	O
are	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
processors	O
.	O
</s>
