<s>
Hardware	B-General_Concept
scout	I-General_Concept
is	O
a	O
technique	O
that	O
uses	O
otherwise	O
idle	O
processor	B-General_Concept
execution	O
resources	O
to	O
perform	O
prefetching	B-General_Concept
during	O
cache	B-General_Concept
misses	O
.	O
</s>
<s>
When	O
a	O
thread	O
is	O
stalled	O
by	O
a	O
cache	B-General_Concept
miss	O
,	O
the	O
processor	B-General_Concept
pipeline	O
checkpoints	O
the	O
register	B-General_Concept
file	I-General_Concept
,	O
switches	O
to	O
runahead	B-General_Concept
mode	O
,	O
and	O
continues	O
to	O
issue	O
instructions	O
from	O
the	O
thread	O
that	O
is	O
waiting	O
for	O
memory	O
.	O
</s>
<s>
When	O
the	O
data	O
returns	O
from	O
memory	O
,	O
the	O
processor	B-General_Concept
restores	O
the	O
register	B-General_Concept
file	I-General_Concept
contents	O
from	O
the	O
checkpoint	O
,	O
and	O
switches	O
back	O
to	O
normal	O
execution	O
mode	O
.	O
</s>
<s>
The	O
computation	O
during	O
run-ahead	O
mode	O
is	O
discarded	O
by	O
the	O
processor	B-General_Concept
;	O
nevertheless	O
,	O
scouting	O
provides	O
speedup	O
because	O
memory	B-Operating_System
level	I-Operating_System
parallelism	I-Operating_System
(	O
MLP	O
)	O
is	O
increased	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
lines	O
brought	O
into	O
the	O
cache	B-General_Concept
hierarchy	O
are	O
often	O
used	O
by	O
the	O
processor	B-General_Concept
again	O
when	O
it	O
switches	O
back	O
to	O
normal	O
mode	O
.	O
</s>
<s>
Sun	O
's	O
Rock	B-Device
processor	I-Device
(	O
later	O
canceled	O
)	O
used	O
a	O
form	O
of	O
hardware	B-General_Concept
scout	I-General_Concept
.	O
</s>
<s>
However	O
,	O
any	O
computations	O
in	O
run-ahead	O
mode	O
that	O
do	O
not	O
depend	O
on	O
the	O
cache	B-General_Concept
miss	O
may	O
be	O
retired	O
immediately	O
.	O
</s>
<s>
This	O
allows	O
both	O
prefetching	B-General_Concept
and	O
traditional	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
.	O
</s>
<s>
Scouting	O
and	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
both	O
use	O
hardware	O
threads	O
to	O
fight	O
the	O
memory	O
wall	O
.	O
</s>
<s>
Thus	O
,	O
SMT	O
increases	O
the	O
throughput	O
of	O
the	O
processor	B-General_Concept
while	O
scouting	O
increases	O
the	O
performance	O
by	O
lowering	O
the	O
number	O
of	O
cache	B-General_Concept
misses	O
.	O
</s>
