<s>
Hardware	B-General_Concept
acceleration	I-General_Concept
is	O
the	O
use	O
of	O
computer	B-Architecture
hardware	I-Architecture
designed	O
to	O
perform	O
specific	O
functions	O
more	O
efficiently	O
when	O
compared	O
to	O
software	O
running	O
on	O
a	O
general-purpose	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
.	O
</s>
<s>
Any	O
transformation	O
of	O
data	B-General_Concept
that	O
can	O
be	O
calculated	O
in	O
software	O
running	O
on	O
a	O
generic	O
CPU	O
can	O
also	O
be	O
calculated	O
in	O
custom-made	O
hardware	B-Architecture
,	O
or	O
in	O
some	O
mix	O
of	O
both	O
.	O
</s>
<s>
To	O
perform	O
computing	O
tasks	O
more	O
quickly	O
(	O
or	O
better	O
in	O
some	O
other	O
way	O
)	O
,	O
generally	O
one	O
can	O
invest	O
time	O
and	O
money	O
in	O
improving	O
the	O
software	O
,	O
improving	O
the	O
hardware	B-Architecture
,	O
or	O
both	O
.	O
</s>
<s>
Typical	O
advantages	O
of	O
focusing	O
on	O
software	O
may	O
include	O
more	O
rapid	O
development	O
,	O
lower	O
non-recurring	O
engineering	O
costs	O
,	O
heightened	O
portability	B-Architecture
,	O
and	O
ease	O
of	O
updating	O
features	O
or	O
patching	O
bugs	B-Error_Name
,	O
at	O
the	O
cost	O
of	O
overhead	O
to	O
compute	O
general	O
operations	O
.	O
</s>
<s>
Advantages	O
of	O
focusing	O
on	O
hardware	B-Architecture
may	O
include	O
speedup	B-Operating_System
,	O
reduced	O
power	O
consumption	O
,	O
lower	O
latency	O
,	O
increased	O
parallelism	B-Operating_System
and	O
bandwidth	O
,	O
and	O
better	O
utilization	O
of	O
area	O
and	O
functional	B-General_Concept
components	I-General_Concept
available	O
on	O
an	O
integrated	O
circuit	O
;	O
at	O
the	O
cost	O
of	O
lower	O
ability	O
to	O
update	O
designs	O
once	O
etched	B-Architecture
onto	I-Architecture
silicon	I-Architecture
and	O
higher	O
costs	O
of	O
functional	O
verification	O
,	O
and	O
times	O
to	O
market	O
.	O
</s>
<s>
In	O
the	O
hierarchy	O
of	O
digital	O
computing	O
systems	O
ranging	O
from	O
general-purpose	O
processors	O
to	O
fully	O
customized	O
hardware	B-Architecture
,	O
there	O
is	O
a	O
tradeoff	O
between	O
flexibility	O
and	O
efficiency	O
,	O
with	O
efficiency	O
increasing	O
by	O
orders	B-Device
of	I-Device
magnitude	I-Device
when	O
any	O
given	O
application	O
is	O
implemented	O
higher	O
up	O
that	O
hierarchy	O
.	O
</s>
<s>
This	O
hierarchy	O
includes	O
general-purpose	O
processors	O
such	O
as	O
CPUs	O
,	O
more	O
specialized	O
processors	O
such	O
as	O
GPUs	B-Architecture
,	O
fixed-function	O
implemented	O
on	O
field-programmable	B-Architecture
gate	I-Architecture
arrays	I-Architecture
(	O
FPGAs	B-Architecture
)	O
,	O
and	O
fixed-function	O
implemented	O
on	O
application-specific	O
integrated	O
circuits	O
(	O
ASICs	O
)	O
.	O
</s>
<s>
Hardware	B-General_Concept
acceleration	I-General_Concept
is	O
advantageous	O
for	O
performance	O
,	O
and	O
practical	O
when	O
the	O
functions	O
are	O
fixed	O
so	O
updates	O
are	O
not	O
as	O
needed	O
as	O
in	O
software	O
solutions	O
.	O
</s>
<s>
With	O
the	O
advent	O
of	O
reprogrammable	B-Architecture
logic	O
devices	O
such	O
as	O
FPGAs	B-Architecture
,	O
the	O
restriction	O
of	O
hardware	B-General_Concept
acceleration	I-General_Concept
to	O
fully	O
fixed	O
algorithms	O
has	O
eased	O
since	O
2010	O
,	O
allowing	O
hardware	B-General_Concept
acceleration	I-General_Concept
to	O
be	O
applied	O
to	O
problem	O
domains	O
requiring	O
modification	O
to	O
algorithms	O
and	O
processing	O
control	O
flow	O
.	O
</s>
<s>
Most	O
often	O
in	O
computing	O
,	O
signals	O
are	O
digital	O
and	O
can	O
be	O
interpreted	O
as	O
binary	O
number	O
data	B-General_Concept
.	O
</s>
<s>
Computer	B-Architecture
hardware	I-Architecture
and	O
software	O
operate	O
on	O
information	O
in	O
binary	O
representation	O
to	O
perform	O
computing	O
;	O
this	O
is	O
accomplished	O
by	O
calculating	O
boolean	O
functions	O
on	O
the	O
bits	O
of	O
input	O
and	O
outputting	O
the	O
result	O
to	O
some	O
output	B-Device
device	I-Device
downstream	O
for	O
storage	B-General_Concept
or	O
further	B-General_Concept
processing	I-General_Concept
.	O
</s>
<s>
Because	O
all	O
Turing	B-Architecture
machines	I-Architecture
can	O
run	O
any	O
computable	O
function	O
,	O
it	O
is	O
always	O
possible	O
to	O
design	O
custom	O
hardware	B-Architecture
that	O
performs	O
the	O
same	O
function	O
as	O
a	O
given	O
piece	O
of	O
software	O
.	O
</s>
<s>
Conversely	O
,	O
software	O
can	O
be	O
always	O
used	O
to	O
emulate	O
the	O
function	O
of	O
a	O
given	O
piece	O
of	O
hardware	B-Architecture
.	O
</s>
<s>
Custom	O
hardware	B-Architecture
may	O
offer	O
higher	O
performance	O
per	O
watt	O
for	O
the	O
same	O
functions	O
that	O
can	O
be	O
specified	O
in	O
software	O
.	O
</s>
<s>
Hardware	B-Architecture
description	O
languages	O
(	O
HDLs	O
)	O
such	O
as	O
Verilog	B-Language
and	O
VHDL	B-Language
can	O
model	O
the	O
same	O
semantics	B-Application
as	O
software	O
and	O
synthesize	O
the	O
design	O
into	O
a	O
netlist	O
that	O
can	O
be	O
programmed	O
to	O
an	O
FPGA	B-Architecture
or	O
composed	O
into	O
the	O
logic	O
gates	O
of	O
an	O
ASIC	O
.	O
</s>
<s>
The	O
vast	O
majority	O
of	O
software-based	O
computing	O
occurs	O
on	O
machines	O
implementing	O
the	O
von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
,	O
collectively	O
known	O
as	O
stored-program	O
computers	O
.	O
</s>
<s>
Computer	B-Application
programs	I-Application
are	O
stored	O
as	O
data	B-General_Concept
and	O
executed	B-General_Concept
by	O
processors	O
.	O
</s>
<s>
Such	O
processors	O
must	O
fetch	O
and	O
decode	O
instructions	O
,	O
as	O
well	O
as	O
loading	B-Architecture
data	I-Architecture
operands	I-Architecture
from	O
memory	B-General_Concept
(	O
as	O
part	O
of	O
the	O
instruction	B-General_Concept
cycle	I-General_Concept
)	O
to	O
execute	O
the	O
instructions	O
constituting	O
the	O
software	B-Application
program	I-Application
.	O
</s>
<s>
Relying	O
on	O
a	O
common	O
cache	B-General_Concept
for	O
code	O
and	O
data	B-General_Concept
leads	O
to	O
the	O
"	O
von	O
Neumann	O
bottleneck	O
"	O
,	O
a	O
fundamental	O
limitation	O
on	O
the	O
throughput	O
of	O
software	O
on	O
processors	O
implementing	O
the	O
von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
.	O
</s>
<s>
Even	O
in	O
the	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
,	O
where	O
instructions	O
and	O
data	B-General_Concept
have	O
separate	O
caches	O
in	O
the	O
memory	B-General_Concept
hierarchy	I-General_Concept
,	O
there	O
is	O
overhead	O
to	O
decoding	O
instruction	B-Language
opcodes	I-Language
and	O
multiplexing	B-Protocol
available	O
execution	B-General_Concept
units	I-General_Concept
on	O
a	O
microprocessor	B-Architecture
or	O
microcontroller	B-Architecture
,	O
leading	O
to	O
low	O
circuit	O
utilization	O
.	O
</s>
<s>
Modern	O
processors	O
that	O
provide	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
exploit	O
under-utilization	O
of	O
available	O
processor	O
functional	B-General_Concept
units	I-General_Concept
and	O
instruction	B-Operating_System
level	I-Operating_System
parallelism	I-Operating_System
between	O
different	O
hardware	B-Architecture
threads	O
.	O
</s>
<s>
Hardware	B-Architecture
execution	B-General_Concept
units	I-General_Concept
do	O
not	O
in	O
general	O
rely	O
on	O
the	O
von	O
Neumann	O
or	O
modified	B-Device
Harvard	I-Device
architectures	I-Device
and	O
do	O
not	O
need	O
to	O
perform	O
the	O
instruction	O
fetch	O
and	O
decode	O
steps	O
of	O
an	O
instruction	B-General_Concept
cycle	I-General_Concept
and	O
incur	O
those	O
stages	O
 '	O
overhead	O
.	O
</s>
<s>
If	O
needed	O
calculations	O
are	O
specified	O
in	O
a	O
register	O
transfer	O
level	O
(	O
RTL	O
)	O
hardware	B-Architecture
design	O
,	O
the	O
time	O
and	O
circuit	O
area	O
costs	O
that	O
would	O
be	O
incurred	O
by	O
instruction	O
fetch	O
and	O
decoding	O
stages	O
can	O
be	O
reclaimed	O
and	O
put	O
to	O
other	O
uses	O
.	O
</s>
<s>
The	O
reclaimed	O
resources	O
can	O
be	O
used	O
for	O
increased	O
parallel	B-Operating_System
computation	I-Operating_System
,	O
other	O
functions	O
,	O
communication	O
or	O
memory	B-General_Concept
,	O
as	O
well	O
as	O
increased	O
input/output	B-General_Concept
capabilities	O
.	O
</s>
<s>
Greater	O
RTL	O
customization	O
of	O
hardware	B-Architecture
designs	O
allows	O
emerging	O
architectures	O
such	O
as	O
in-memory	B-General_Concept
computing	I-General_Concept
,	O
transport	B-General_Concept
triggered	I-General_Concept
architectures	I-General_Concept
(	O
TTA	O
)	O
and	O
networks-on-chip	B-Architecture
(	O
NoC	B-Architecture
)	O
to	O
further	O
benefit	O
from	O
increased	O
locality	B-General_Concept
of	O
data	B-General_Concept
to	O
execution	O
context	O
,	O
thereby	O
reducing	O
computing	O
and	O
communication	O
latency	O
between	O
modules	O
and	O
functional	B-General_Concept
units	I-General_Concept
.	O
</s>
<s>
Custom	O
hardware	B-Architecture
is	O
limited	O
in	O
parallel	B-Operating_System
processing	I-Operating_System
capability	O
only	O
by	O
the	O
area	O
and	O
logic	O
blocks	O
available	O
on	O
the	O
integrated	O
circuit	O
die	O
.	O
</s>
<s>
Therefore	O
,	O
hardware	B-Architecture
is	O
much	O
more	O
free	O
to	O
offer	O
massive	B-Operating_System
parallelism	I-Operating_System
than	O
software	O
on	O
general-purpose	O
processors	O
,	O
offering	O
a	O
possibility	O
of	O
implementing	O
the	O
parallel	B-Operating_System
random-access	I-Operating_System
machine	I-Operating_System
(	O
PRAM	O
)	O
model	O
.	O
</s>
<s>
It	O
is	O
common	O
to	O
build	O
multicore	B-Architecture
and	O
manycore	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
out	O
of	O
microprocessor	B-Device
IP	I-Device
core	I-Device
schematics	I-Device
on	O
a	O
single	O
FPGA	B-Architecture
or	O
ASIC	O
.	O
</s>
<s>
Similarly	O
,	O
specialized	O
functional	B-General_Concept
units	I-General_Concept
can	O
be	O
composed	O
in	O
parallel	O
as	O
in	B-Operating_System
digital	I-Operating_System
signal	I-Operating_System
processing	I-Operating_System
without	O
being	O
embedded	O
in	O
a	O
processor	O
IP	B-Architecture
core	I-Architecture
.	O
</s>
<s>
Therefore	O
,	O
hardware	B-General_Concept
acceleration	I-General_Concept
is	O
often	O
employed	O
for	O
repetitive	O
,	O
fixed	O
tasks	O
involving	O
little	O
conditional	B-Language
branching	I-Language
,	O
especially	O
on	O
large	O
amounts	O
of	O
data	B-General_Concept
.	O
</s>
<s>
This	O
is	O
how	O
Nvidia	O
's	O
CUDA	B-Architecture
line	O
of	O
GPUs	B-Architecture
are	O
implemented	O
.	O
</s>
<s>
As	O
device	O
mobility	O
has	O
increased	O
,	O
new	O
metrics	O
have	O
been	O
developed	O
that	O
measure	O
the	O
relative	O
performance	O
of	O
specific	O
acceleration	O
protocols	O
,	O
considering	O
the	O
characteristics	O
such	O
as	O
physical	O
hardware	B-Architecture
dimensions	O
,	O
power	O
consumption	O
and	O
operations	O
throughput	O
.	O
</s>
<s>
Appropriate	O
metrics	O
consider	O
the	O
area	O
of	O
the	O
hardware	B-Architecture
along	O
with	O
both	O
the	O
corresponding	O
operations	O
throughput	O
and	O
energy	O
consumed	O
.	O
</s>
<s>
Examples	O
of	O
hardware	B-General_Concept
acceleration	I-General_Concept
include	O
bit	B-Algorithm
blit	I-Algorithm
acceleration	O
functionality	O
in	O
graphics	B-Architecture
processing	I-Architecture
units	I-Architecture
(	O
GPUs	B-Architecture
)	O
,	O
use	O
of	O
memristors	O
for	O
accelerating	O
neural	B-Architecture
networks	I-Architecture
and	O
regular	B-Language
expression	I-Language
hardware	B-General_Concept
acceleration	I-General_Concept
for	O
spam	O
control	O
in	O
the	O
server	B-Application
industry	O
,	O
intended	O
to	O
prevent	O
regular	B-Algorithm
expression	I-Algorithm
denial	I-Algorithm
of	I-Algorithm
service	I-Algorithm
(	O
ReDoS	B-Algorithm
)	O
attacks	O
.	O
</s>
<s>
The	O
hardware	B-Architecture
that	O
performs	O
the	O
acceleration	O
may	O
be	O
part	O
of	O
a	O
general-purpose	O
CPU	O
,	O
or	O
a	O
separate	O
unit	O
called	O
a	O
hardware	B-General_Concept
accelerator	I-General_Concept
,	O
though	O
they	O
are	O
usually	O
referred	O
with	O
a	O
more	O
specific	O
term	O
,	O
such	O
as	O
3D	B-Architecture
accelerator	I-Architecture
,	O
or	O
cryptographic	B-General_Concept
accelerator	I-General_Concept
.	O
</s>
<s>
Traditionally	O
,	O
processors	O
were	O
sequential	O
(	O
instructions	O
are	O
executed	B-General_Concept
one	O
by	O
one	O
)	O
,	O
and	O
were	O
designed	O
to	O
run	O
general	O
purpose	O
algorithms	O
controlled	O
by	O
instruction	O
fetch	O
(	O
for	O
example	O
moving	O
temporary	O
results	O
to	B-Architecture
and	I-Architecture
from	I-Architecture
a	O
register	B-General_Concept
file	I-General_Concept
)	O
.	O
</s>
<s>
Hardware	B-General_Concept
accelerators	I-General_Concept
improve	O
the	O
execution	O
of	O
a	O
specific	O
algorithm	O
by	O
allowing	O
greater	O
concurrency	B-Operating_System
,	O
having	O
specific	O
datapaths	B-General_Concept
for	O
their	O
temporary	O
variables	O
,	O
and	O
reducing	O
the	O
overhead	O
of	O
instruction	O
control	O
in	O
the	O
fetch-decode-execute	B-General_Concept
cycle	I-General_Concept
.	O
</s>
<s>
Modern	O
processors	O
are	O
multi-core	B-Architecture
and	O
often	O
feature	O
parallel	O
"	O
single-instruction	O
;	O
multiple	O
data	B-General_Concept
"	O
(	O
SIMD	B-Device
)	O
units	O
.	O
</s>
<s>
Even	O
so	O
,	O
hardware	B-General_Concept
acceleration	I-General_Concept
still	O
yields	O
benefits	O
.	O
</s>
<s>
Hardware	B-General_Concept
acceleration	I-General_Concept
is	O
suitable	O
for	O
any	O
computation-intensive	O
algorithm	O
which	O
is	O
executed	B-General_Concept
frequently	O
in	O
a	O
task	O
or	O
program	O
.	O
</s>
<s>
Depending	O
upon	O
the	O
granularity	O
,	O
hardware	B-General_Concept
acceleration	I-General_Concept
can	O
vary	O
from	O
a	O
small	O
functional	B-General_Concept
unit	I-General_Concept
,	O
to	O
a	O
large	O
functional	O
block	O
(	O
like	O
motion	O
estimation	O
in	O
MPEG-2	B-Algorithm
)	O
.	O
</s>
<s>
"	O
Hardware	B-General_Concept
accelerated	I-General_Concept
convolutional	O
neural	B-Architecture
networks	I-Architecture
for	O
synthetic	O
vision	O
systems.	O
"	O
</s>
