<s>
The	O
HITAC	B-Device
S-810	I-Device
is	O
a	O
family	O
of	O
vector	B-Operating_System
supercomputers	B-Architecture
developed	O
,	O
manufactured	O
and	O
marketed	O
by	O
Hitachi	O
.	O
</s>
<s>
The	O
S-810	O
,	O
first	O
announced	O
in	O
August	O
1982	O
,	O
was	O
the	O
second	O
Japanese	O
supercomputer	B-Architecture
,	O
following	O
the	O
Fujitsu	O
VP-200	O
(	O
July	O
1982	O
)	O
but	O
predating	O
the	O
NEC	B-Device
SX-2	I-Device
(	O
April	O
1983	O
)	O
.	O
</s>
<s>
The	O
S-810	O
was	O
Hitachi	O
's	O
first	O
supercomputer	B-Architecture
,	O
although	O
the	O
company	O
had	O
previously	O
built	O
a	O
vector	B-Operating_System
processor	I-Operating_System
,	O
the	O
IAP	O
.	O
</s>
<s>
The	O
S-810	O
was	O
succeeded	O
as	O
Hitachi	O
's	O
top-end	O
supercomputer	B-Architecture
by	O
the	O
HITAC	B-Device
S-820	I-Device
announced	O
in	O
July	O
1987	O
.	O
</s>
<s>
The	O
S-810	O
implements	O
a	O
Hitachi-designed	O
extension	O
of	O
the	O
IBM	B-Device
System/370	I-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
with	O
83	O
vector	B-Operating_System
instructions	O
(	O
80	O
in	O
the	O
S-810/5	O
and	O
S-810/10	O
)	O
.	O
</s>
<s>
The	O
vector	B-Operating_System
instructions	O
are	O
register-to-register	O
,	O
meaning	O
that	O
they	O
do	O
not	O
directly	O
reference	O
memory	O
.	O
</s>
<s>
The	O
scalar	B-General_Concept
processor	I-General_Concept
is	O
a	O
Hitachi	O
HITAC	O
M-280H	O
mainframe	B-Architecture
with	O
a	O
28nanosecond	O
(	O
ns	O
)	O
cycle	B-General_Concept
time	I-General_Concept
(	O
clock	O
rate	O
of	O
approximately	O
35.71MHz	O
)	O
.	O
</s>
<s>
In	O
all	O
models	O
,	O
the	O
scalar	B-General_Concept
processor	I-General_Concept
has	O
a	O
large	O
256kilobyte	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
vector	B-Operating_System
processor	I-Operating_System
has	O
a	O
14ns	O
cycle	B-General_Concept
time	I-General_Concept
(	O
clock	O
rate	O
of	O
approximately	O
71.43MHz	O
)	O
.	O
</s>
<s>
The	O
vector	B-Operating_System
registers	O
are	O
256	O
elements	O
wide	O
,	O
and	O
each	O
element	O
is	O
64	O
bits	O
wide	O
.	O
</s>
<s>
These	O
registers	O
are	O
implemented	O
with	O
1kilobit	O
(	O
Kbit	O
)	O
bipolar	O
RAM	O
integrated	O
circuits	O
(	O
ICs	O
)	O
with	O
a	O
4.5ns	O
access	B-General_Concept
time	I-General_Concept
.	O
</s>
<s>
All	O
models	O
have	O
eight	O
256-bit	O
vector	B-Operating_System
mask	O
registers	O
and	O
48	O
vector	B-Operating_System
address	O
registers	O
.	O
</s>
<s>
The	O
S-810/20	O
has	O
two	O
lanes	O
,	O
each	O
with	O
two	O
add	O
,	O
one	O
multiply	O
followed	O
by	O
add	O
,	O
and	O
one	O
multiply	O
or	O
divide	O
followed	O
by	O
add	O
floating	B-Algorithm
point	I-Algorithm
pipelines	O
,	O
for	O
a	O
total	O
of	O
twelve	O
.	O
</s>
<s>
CPU	O
logic	O
is	O
implemented	O
with	O
two	O
emitter-coupled	B-General_Concept
logic	I-General_Concept
gate	O
array	O
IC	O
types	O
,	O
a	O
550-gate	O
part	O
with	O
a	O
250picosecond	O
(	O
ps	O
)	O
gate	O
delay	O
and	O
a	O
1,500	O
-gate	O
part	O
with	O
a	O
450ps	O
gate	O
delay	O
.	O
</s>
<s>
The	O
main	O
memory	O
is	O
implemented	O
with	O
16Kbit	O
complementary	O
metal	O
–	O
oxide	O
–	O
semiconductor	O
static	B-Architecture
random	I-Architecture
access	I-Architecture
memory	I-Architecture
ICs	O
with	O
an	O
access	B-General_Concept
time	I-General_Concept
of	O
40ns	O
.	O
</s>
<s>
They	O
differ	O
in	O
the	O
number	O
of	O
vector	B-Operating_System
pipelines	O
installed	O
,	O
the	O
number	O
of	O
scalar	O
registers	O
,	O
the	O
number	O
vector	B-Operating_System
registers	O
,	O
and	O
the	O
amount	O
of	O
memory	O
supported	O
.	O
</s>
