<s>
SPARC64	B-General_Concept
is	I-General_Concept
a	O
microprocessor	B-Architecture
developed	O
by	O
HAL	O
Computer	O
Systems	O
and	O
fabricated	O
by	O
Fujitsu	O
.	O
</s>
<s>
It	O
implements	O
the	O
SPARC	B-Architecture
V9	I-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
,	O
the	O
first	O
microprocessor	B-Architecture
to	O
do	O
so	O
.	O
</s>
<s>
SPARC64	O
was	O
HAL	O
's	O
first	O
microprocessor	B-Architecture
and	O
was	O
the	O
first	O
in	O
the	O
SPARC64	O
brand	O
.	O
</s>
<s>
It	O
was	O
succeeded	O
by	O
the	O
SPARC64	B-General_Concept
II	I-General_Concept
(	O
previously	O
known	O
as	O
the	O
SPARC64+	B-General_Concept
)	O
in	O
1996	O
.	O
</s>
<s>
The	O
SPARC64	B-General_Concept
is	I-General_Concept
a	O
superscalar	B-General_Concept
microprocessor	B-Architecture
that	O
issues	O
four	O
instructions	O
per	O
cycle	O
and	O
executes	O
them	O
out	B-General_Concept
of	I-General_Concept
order	I-General_Concept
.	O
</s>
<s>
But	O
the	O
FMA	O
instructions	O
are	O
really	O
fused	O
(	O
that	O
is	O
,	O
with	O
a	O
single	O
rounding	O
)	O
only	O
as	O
of	O
SPARC64	B-Device
VI	I-Device
.	O
</s>
<s>
The	O
MMU	O
die	O
contains	O
the	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
,	O
cache	O
controller	O
and	O
the	O
external	O
interfaces	O
.	O
</s>
<s>
The	O
seven	O
dies	O
are	O
packaged	O
in	O
a	O
rectangular	O
ceramic	O
multi-chip	B-Algorithm
module	I-Algorithm
(	O
MCM	O
)	O
,	O
connected	O
to	O
the	O
underside	O
of	O
the	O
MCM	O
with	O
solder	O
bumps	O
.	O
</s>
<s>
The	O
MCM	O
has	O
565	O
pins	O
,	O
of	O
which	O
286	O
are	O
signal	O
pins	O
and	O
218	O
are	O
power	O
pins	O
,	O
organized	O
as	O
a	O
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
PGA	O
)	O
.	O
</s>
<s>
The	O
SPARC64	B-General_Concept
II	I-General_Concept
(	O
SPARC64+	B-General_Concept
)	O
was	O
a	O
further	O
development	O
of	O
the	O
SPARC64	O
.	O
</s>
<s>
It	O
is	O
a	O
second-generation	O
SPARC64	O
microprocessor	B-Architecture
.	O
</s>
<s>
The	O
SPARC64	B-General_Concept
II	I-General_Concept
was	O
succeeded	O
by	O
the	O
SPARC64	B-General_Concept
III	I-General_Concept
in	O
1998	O
.	O
</s>
<s>
The	O
SPARC64	B-General_Concept
II	I-General_Concept
has	O
higher	O
performance	O
due	O
to	O
higher	O
clock	O
frequencies	O
enabled	O
by	O
the	O
new	O
process	O
and	O
circuit	O
tweaks	O
;	O
and	O
a	O
higher	O
instructions	O
per	O
cycle	O
(	O
IPC	O
)	O
count	O
due	O
to	O
the	O
following	O
microarchitecture	O
improvements	O
:	O
</s>
<s>
The	O
SPARC64	B-General_Concept
GP	I-General_Concept
is	O
a	O
series	O
of	O
related	O
microprocessors	B-Architecture
developed	O
by	O
HAL	O
and	O
Fujitsu	O
used	O
in	O
the	O
Fujitsu	O
GP7000F	O
and	O
PrimePower	O
servers	B-Application
.	O
</s>
<s>
The	O
first	O
SPARC64	B-General_Concept
GP	I-General_Concept
was	O
a	O
further	O
development	O
of	O
the	O
SPARC64	B-General_Concept
II	I-General_Concept
.	O
</s>
<s>
It	O
was	O
a	O
third-generation	O
SPARC64	O
microprocessor	B-Architecture
and	O
was	O
known	O
as	O
the	O
SPARC64	B-General_Concept
III	I-General_Concept
before	O
it	O
was	O
introduced	O
.	O
</s>
<s>
The	O
SPARC64	B-General_Concept
GP	I-General_Concept
operated	O
at	O
clock	O
frequencies	O
of	O
225	O
,	O
250	O
and	O
275MHz	O
.	O
</s>
<s>
It	O
was	O
the	O
first	O
microprocessor	B-Architecture
from	O
HAL	O
to	O
support	O
multiprocessing	B-Operating_System
.	O
</s>
<s>
The	O
main	O
competitors	O
were	O
the	O
HP	O
PA-8500	B-General_Concept
,	O
IBM	O
POWER3	B-General_Concept
and	O
Sun	O
UltraSPARC	B-General_Concept
II	I-General_Concept
.	O
</s>
<s>
The	O
SPARC64	B-General_Concept
GP	I-General_Concept
was	O
taped	O
out	O
in	O
July	O
1997	O
.	O
</s>
<s>
It	O
was	O
a	O
single-die	O
implementation	O
of	O
the	O
SPARC64	B-General_Concept
II	I-General_Concept
that	O
integrated	O
,	O
with	O
modifications	O
,	O
the	O
CPU	O
die	O
and	O
two	O
of	O
the	O
four	O
CACHE	O
dies	O
.	O
</s>
<s>
Numerous	O
modifications	O
and	O
improvements	O
were	O
made	O
to	O
the	O
microarchitecture	O
,	O
such	O
as	O
the	O
replacement	O
of	O
the	O
MMU	O
and	O
a	O
new	O
system	O
interface	O
using	O
the	O
Ultra	B-Architecture
Port	I-Architecture
Architecture	I-Architecture
.	O
</s>
<s>
It	O
had	O
improved	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
an	O
extra	O
pipeline	O
stage	O
to	O
improve	O
clock	O
frequencies	O
and	O
a	O
second	O
FPU	O
which	O
could	O
execute	O
add	O
and	O
subtract	O
instructions	O
.	O
</s>
<s>
The	O
complex	O
SPARC64	B-General_Concept
II	I-General_Concept
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
was	O
replaced	O
with	O
a	O
simpler	O
one	O
that	O
is	O
compatible	O
with	O
the	O
Solaris	B-Application
operating	I-Application
system	I-Application
.	O
</s>
<s>
Previously	O
,	O
SPARC64	O
systems	O
ran	O
SPARC64/OS	O
,	O
a	O
derivative	O
of	O
Solaris	B-Application
developed	O
by	O
HAL	O
that	O
supported	O
the	O
SPARC64	O
.	O
</s>
<s>
The	O
L1	O
caches	O
were	O
halved	O
in	O
capacity	O
to	O
64KB	O
from	O
128KB	O
to	O
reduce	O
die	O
area	O
(	O
the	O
reason	O
why	O
only	O
two	O
of	O
the	O
four	O
CACHE	O
dies	O
were	O
integrated	O
from	O
the	O
SPARC64	B-General_Concept
II	I-General_Concept
)	O
.	O
</s>
<s>
The	O
L2	O
cache	O
is	O
accessed	O
with	O
a	O
dedicated	O
128-bit	O
data	O
bus	O
that	O
operates	O
at	O
the	O
same	O
or	O
half	O
clock	O
frequency	O
of	O
the	O
microprocessor	B-Architecture
.	O
</s>
<s>
The	O
SPARC64	B-General_Concept
II	I-General_Concept
's	O
proprietary	O
system	O
interface	O
was	O
replaced	O
by	O
one	O
compatible	O
with	O
the	O
Ultra	B-Architecture
Port	I-Architecture
Architecture	I-Architecture
.	O
</s>
<s>
This	O
enabled	O
the	O
SPARC64	B-General_Concept
III	I-General_Concept
to	O
use	O
chipsets	O
from	O
Sun	O
Microelectronics	O
.	O
</s>
<s>
The	O
system	O
bus	O
operates	O
at	O
half	O
,	O
a	O
third	O
,	O
quarter	O
or	O
fifth	O
the	O
frequency	O
of	O
the	O
microprocessor	B-Architecture
,	O
up	O
to	O
a	O
maximum	O
of	O
150MHz	O
.	O
</s>
<s>
The	O
Ultra	B-Architecture
Port	I-Architecture
Architecture	I-Architecture
(	O
UPA	O
)	O
signals	O
are	O
compatible	O
with	O
3.3	O
V	O
Low	O
Voltage	O
Transistor	O
Transistor	O
Logic	O
(	O
LVTTL	O
)	O
levels	O
with	O
the	O
exception	O
of	O
differential	O
clock	O
signals	O
which	O
are	O
compatible	O
with	O
3.3	O
V	O
pseudo	O
emitter	O
coupled	O
logic	O
(	O
PECL	O
)	O
levels	O
.	O
</s>
<s>
The	O
second	O
and	O
third	O
SPARC64	B-General_Concept
GPs	I-General_Concept
are	O
fourth	O
generation	O
SPARC64	O
microprocessors	B-Architecture
.	O
</s>
<s>
The	O
second	O
SPARC64	B-General_Concept
GP	I-General_Concept
was	O
a	O
further	O
development	O
of	O
the	O
first	O
and	O
it	O
operated	O
at	O
400	O
to	O
563MHz	O
.	O
</s>
<s>
It	O
had	O
larger	O
L1	O
instruction	O
and	O
data	O
caches	O
,	O
doubled	O
in	O
capacity	O
to	O
128KB	O
each	O
;	O
better	O
branch	B-General_Concept
prediction	I-General_Concept
as	O
the	O
result	O
of	O
a	O
larger	O
BHT	O
consisting	O
of	O
16,384	O
entries	O
;	O
support	O
for	O
the	O
Visual	B-General_Concept
Instruction	I-General_Concept
Set	I-General_Concept
(	O
VIS	O
)	O
;	O
and	O
a	O
L2	O
cache	O
built	O
from	O
double	O
data	O
rate	O
(	O
DDR	O
)	O
SRAM	O
.	O
</s>
<s>
It	O
was	O
packaged	O
in	O
a	O
1,206	O
-contact	O
ball	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
BGA	O
)	O
measuring	O
37.5mm	O
by	O
37.5mm	O
.	O
</s>
<s>
The	O
third	O
SPARC64	B-General_Concept
GP	I-General_Concept
was	O
identical	O
to	O
the	O
second	O
in	O
terms	O
of	O
microarchitecture	O
.	O
</s>
