<s>
Graphics	B-Architecture
Core	I-Architecture
Next	I-Architecture
(	O
GCN	O
)	O
is	O
the	O
codename	O
for	O
a	O
series	O
of	O
microarchitectures	B-General_Concept
and	O
an	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
that	O
were	O
developed	O
by	O
AMD	O
for	O
its	O
GPUs	B-Architecture
as	O
the	O
successor	O
to	O
its	O
TeraScale	B-Architecture
microarchitecture	B-General_Concept
.	O
</s>
<s>
GCN	O
is	O
a	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
SIMD	B-Device
microarchitecture	B-General_Concept
contrasting	O
the	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
SIMD	B-Device
architecture	O
of	O
TeraScale	B-Architecture
.	O
</s>
<s>
GCN	O
requires	O
considerably	O
more	O
transistors	B-Application
than	O
TeraScale	B-Architecture
,	O
but	O
offers	O
advantages	O
for	O
general-purpose	B-Architecture
GPU	I-Architecture
(	O
GPGPU	B-Architecture
)	O
computation	O
due	O
to	O
a	O
simpler	O
compiler	B-Language
.	O
</s>
<s>
GCN	O
graphics	O
chips	O
were	O
fabricated	B-Architecture
with	O
CMOS	B-Device
at	O
28	O
nm	O
,	O
and	O
with	O
FinFET	O
at	O
14	B-Algorithm
nm	I-Algorithm
(	O
by	O
Samsung	O
Electronics	O
and	O
GlobalFoundries	O
)	O
and	O
7	B-Algorithm
nm	I-Algorithm
(	O
by	O
TSMC	O
)	O
,	O
available	O
on	O
selected	O
models	O
in	O
AMD	O
's	O
Radeon	B-Device
HD	I-Device
7000	O
,	O
HD	B-General_Concept
8000	I-General_Concept
,	O
200	B-Device
,	O
300	B-Device
,	O
400	B-Device
,	O
500	B-Device
and	O
Vega	B-Device
series	O
of	O
graphics	B-Device
cards	I-Device
,	O
including	O
the	O
separately	O
released	O
Radeon	B-Device
VII	O
.	O
</s>
<s>
GCN	O
was	O
also	O
used	O
in	O
the	O
graphics	O
portion	O
of	O
Accelerated	B-Architecture
Processing	I-Architecture
Units	I-Architecture
(	O
APUs	O
)	O
,	O
such	O
as	O
those	O
in	O
the	O
PlayStation	O
4	O
and	O
Xbox	O
One	O
.	O
</s>
<s>
The	O
GCN	O
instruction	B-General_Concept
set	I-General_Concept
is	O
owned	O
by	O
AMD	O
and	O
was	O
developed	O
specifically	O
for	O
GPUs	B-Architecture
.	O
</s>
<s>
It	O
has	O
no	O
micro-operation	B-General_Concept
for	O
division	O
.	O
</s>
<s>
the	O
(	O
also	O
referred	O
to	O
as	O
Graphics	B-Architecture
Core	I-Architecture
Next	I-Architecture
5.1	O
)	O
.	O
</s>
<s>
An	O
LLVM	O
compiler	B-Language
back	O
end	O
is	O
available	O
for	O
the	O
GCN	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
It	O
is	O
used	O
by	O
Mesa	B-Application
3D	I-Application
.	O
</s>
<s>
GNU	B-Application
Compiler	I-Application
Collection	I-Application
9	O
supports	O
GCN	O
3	O
and	O
GCN	O
5	O
since	O
2019	O
for	O
single-threaded	B-Operating_System
,	O
stand-alone	O
programs	O
,	O
with	O
GCC	B-Application
10	O
also	O
offloading	O
via	O
OpenMP	B-Application
and	O
OpenACC	B-Operating_System
.	O
</s>
<s>
MIAOW	O
is	O
an	O
open-source	O
RTL	B-Application
implementation	O
of	O
the	O
AMD	O
Southern	O
Islands	O
GPGPU	B-Architecture
microarchitecture	B-General_Concept
.	O
</s>
<s>
In	O
November	O
2015	O
,	O
AMD	O
announced	O
its	O
Boltzmann	O
Initiative	O
,	O
which	O
aims	O
to	O
enable	O
the	O
porting	O
of	O
CUDA-based	O
applications	O
to	O
a	O
common	O
C++	B-Language
programming	O
model	O
.	O
</s>
<s>
At	O
the	O
Super	O
Computing	O
15	O
event	O
,	O
AMD	O
displayed	O
a	O
Heterogeneous	O
Compute	O
Compiler	B-Language
(	O
HCC	O
)	O
,	O
a	O
headless	O
Linux	B-Application
driver	B-Application
and	O
HSA	B-Architecture
runtime	O
infrastructure	O
for	O
cluster-class	O
high-performance	O
computing	O
,	O
and	O
a	O
Heterogeneous-compute	O
Interface	O
for	O
Portability	O
(	O
HIP	O
)	O
tool	O
for	O
porting	O
CUDA	B-Architecture
applications	O
to	O
the	O
aforementioned	O
common	O
C++	B-Language
model	O
.	O
</s>
<s>
As	O
of	O
July	O
2017	O
,	O
the	O
Graphics	B-Architecture
Core	I-Architecture
Next	I-Architecture
instruction	B-General_Concept
set	I-General_Concept
has	O
seen	O
five	O
iterations	O
.	O
</s>
<s>
The	O
Graphics	O
Command	O
Processor	O
(	O
GCP	O
)	O
is	O
a	O
functional	O
unit	O
of	O
the	O
GCN	O
microarchitecture	B-General_Concept
.	O
</s>
<s>
For	O
a	O
given	O
shader	O
,	O
the	O
GPU	B-Architecture
drivers	O
may	O
also	O
schedule	O
instructions	O
on	O
the	O
CPU	B-General_Concept
to	O
minimize	O
latency	O
.	O
</s>
<s>
The	O
Tesselator	O
is	O
capable	O
of	O
doing	O
tessellation	B-Algorithm
in	O
hardware	O
as	O
defined	O
by	O
Direct3D	B-Application
11	O
and	O
OpenGL	B-Application
4.5	O
(	O
see	O
AMD	O
January	O
21	O
,	O
2017	O
)	O
,	O
and	O
succeeded	O
ATI	O
TruForm	O
and	O
hardware	O
tessellation	B-Algorithm
in	O
TeraScale	B-Architecture
as	O
AMD	O
's	O
then-latest	O
semiconductor	B-Architecture
intellectual	I-Architecture
property	I-Architecture
core	I-Architecture
.	O
</s>
<s>
One	O
compute	O
unit	O
(	O
CU	O
)	O
combines	O
64	O
shader	O
processors	O
with	O
4	O
texture	B-General_Concept
mapping	I-General_Concept
units	I-General_Concept
(	O
TMUs	O
)	O
.	O
</s>
<s>
The	O
compute	O
units	O
are	O
separate	O
from	O
,	O
but	O
feed	O
into	O
,	O
the	O
render	B-General_Concept
output	I-General_Concept
units	I-General_Concept
(	O
ROPs	B-General_Concept
)	O
.	O
</s>
<s>
Four	O
Compute	O
units	O
are	O
wired	O
to	O
share	O
a	O
16KiB	O
L1	O
instruction	O
cache	B-General_Concept
and	O
a	O
32KiB	O
L1	O
data	B-General_Concept
cache	I-General_Concept
,	O
both	O
of	O
which	O
are	O
read-only	O
.	O
</s>
<s>
A	O
SIMD-VU	O
operates	O
on	O
16	O
elements	O
at	O
a	O
time	O
(	O
per	O
cycle	O
)	O
,	O
while	O
a	O
SU	O
can	O
operate	O
on	O
one	O
a	O
time	O
(	O
one/cycle	O
)	O
.	O
</s>
<s>
Every	O
SIMD-VU	O
has	O
some	O
private	O
memory	O
where	O
it	O
stores	O
its	O
registers	O
.	O
</s>
<s>
Every	O
SIMD-VU	O
has	O
room	O
for	O
512	O
scalar	O
registers	O
and	O
256	O
vector	O
registers	O
.	O
</s>
<s>
The	O
CU	O
scheduler	O
is	O
the	O
hardware	O
functional	O
block	O
,	O
choosing	O
which	O
wavefronts	O
the	O
SIMD-VU	O
executes	O
.	O
</s>
<s>
It	O
picks	O
one	O
SIMD-VU	O
per	O
cycle	O
for	O
scheduling	O
.	O
</s>
<s>
A	O
shader	O
is	O
a	O
small	O
program	O
written	O
in	O
GLSL	B-Language
that	O
performs	O
graphics	O
processing	O
,	O
and	O
a	O
kernel	B-Operating_System
is	O
a	O
small	O
program	O
written	O
in	O
OpenCL	O
that	O
performs	O
GPGPU	B-Architecture
processing	O
.	O
</s>
<s>
AMD	O
and	O
Nvidia	O
chose	O
similar	O
approaches	O
to	O
hide	O
this	O
unavoidable	O
latency	O
:	O
the	O
grouping	O
of	O
multiple	O
threads	B-Operating_System
.	O
</s>
<s>
A	O
group	O
of	O
threads	B-Operating_System
is	O
the	O
most	O
basic	O
unit	O
of	O
scheduling	O
of	O
GPUs	B-Architecture
that	O
implement	O
this	O
approach	O
to	O
hide	O
latency	O
.	O
</s>
<s>
It	O
is	O
the	O
minimum	O
size	O
of	O
the	O
data	O
processed	O
in	O
SIMD	B-Device
fashion	O
,	O
the	O
smallest	O
executable	O
unit	O
of	O
code	O
,	O
and	O
the	O
way	O
to	O
processes	O
a	O
single	O
instruction	O
over	O
all	O
of	O
the	O
threads	B-Operating_System
in	O
it	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
In	O
all	O
GCN	O
GPUs	B-Architecture
,	O
a	O
"	O
wavefront	O
"	O
consists	O
of	O
64	O
threads	B-Operating_System
,	O
and	O
in	O
all	O
Nvidia	O
GPUs	B-Architecture
,	O
a	O
"	O
warp	O
"	O
consists	O
of	O
32	O
threads	B-Operating_System
.	O
</s>
<s>
AMD	O
's	O
solution	O
is	O
to	O
attribute	O
multiple	O
wavefronts	O
to	O
each	O
SIMD-VU	O
.	O
</s>
<s>
The	O
hardware	O
distributes	O
the	O
registers	O
to	O
the	O
different	O
wavefronts	O
,	O
and	O
when	O
one	O
wavefront	O
is	O
waiting	O
on	O
some	O
result	O
,	O
which	O
lies	O
in	O
memory	O
,	O
the	O
CU	O
Scheduler	O
assigns	O
the	O
SIMD-VU	O
another	O
wavefront	O
.	O
</s>
<s>
Wavefronts	O
are	O
attributed	O
per	O
SIMD-VU	O
.	O
</s>
<s>
SIMD-VUs	O
do	O
not	O
exchange	O
wavefronts	O
.	O
</s>
<s>
A	O
maximum	O
of	O
10	O
wavefronts	O
can	O
be	O
attributed	O
per	O
SIMD-VU	O
(	O
thus	O
40	O
per	O
CU	O
)	O
.	O
</s>
<s>
AMD	B-Language
CodeXL	I-Language
shows	O
tables	O
with	O
the	O
relationship	O
between	O
number	O
of	O
SGPRs	O
and	O
VGPRs	O
to	O
the	O
number	O
of	O
wavefronts	O
,	O
but	O
essentially	O
,	O
for	O
SGPRS	O
it	O
is	O
between	O
104	O
and	O
512	O
per	O
number	O
of	O
wavefronts	O
,	O
and	O
for	O
VGPRS	O
it	O
is	O
256	O
per	O
number	O
of	O
wavefronts	O
.	O
</s>
<s>
Note	O
that	O
in	O
conjunction	O
with	O
the	O
SSE	B-General_Concept
instructions	I-General_Concept
,	O
this	O
concept	O
of	O
the	O
most	O
basic	O
level	O
of	O
parallelism	O
is	O
often	O
called	O
a	O
"	O
vector	O
width	O
"	O
.	O
</s>
<s>
Each	O
SIMD	B-Device
Vector	O
Unit	O
has	O
:	O
</s>
<s>
Each	O
SIMD-VU	O
has	O
10	O
wavefront	O
instruction	O
buffers	O
,	O
and	O
it	O
takes	O
4	O
cycles	O
to	O
execute	O
one	O
wavefront	O
.	O
</s>
<s>
The	O
Video	O
Coding	O
Engine	O
is	O
a	O
video	O
encoding	O
ASIC	O
,	O
first	O
introduced	O
with	O
the	O
Radeon	B-Device
HD	I-Device
7000	O
Series	O
.	O
</s>
<s>
The	O
initial	O
version	O
of	O
the	O
VCE	O
added	O
support	O
for	O
encoding	O
I	O
and	O
P	O
frames	O
H.264	B-Application
in	O
the	O
YUV420	O
pixel	O
format	O
,	O
along	O
with	O
SVE	O
temporal	O
encode	O
and	O
Display	O
Encode	O
Mode	O
,	O
while	O
the	O
second	O
version	O
added	O
B-frame	O
support	O
for	O
YUV420	O
and	O
YUV444	O
I-frames	O
.	O
</s>
<s>
VCE	O
3.0	O
formed	O
a	O
part	O
of	O
the	O
third	O
generation	O
of	O
GCN	O
,	O
adding	O
high-quality	O
video	O
scaling	O
and	O
the	O
HEVC	B-Algorithm
(	O
H.265	B-Algorithm
)	O
codec	O
.	O
</s>
<s>
VCE	O
4.0	O
was	O
part	O
of	O
the	O
Vega	B-Device
architecture	O
,	O
and	O
was	O
subsequently	O
succeeded	O
by	O
Video	O
Core	O
Next	O
.	O
</s>
<s>
In	O
a	O
preview	O
in	O
2011	O
,	O
AnandTech	O
wrote	O
about	O
the	O
unified	O
virtual	O
memory	O
,	O
supported	O
by	O
Graphics	B-Architecture
Core	I-Architecture
Next	I-Architecture
.	O
</s>
<s>
Some	O
of	O
the	O
specific	O
HSA	B-Architecture
features	O
implemented	O
in	O
the	O
hardware	O
need	O
support	O
from	O
the	O
operating	O
system	O
's	O
kernel	B-Operating_System
(	O
its	O
subsystems	O
)	O
and/or	O
from	O
specific	O
device	B-Application
drivers	I-Application
.	O
</s>
<s>
For	O
example	O
,	O
in	O
July	O
2014	O
,	O
AMD	O
published	O
a	O
set	O
of	O
83	O
patches	O
to	O
be	O
merged	O
into	O
Linux	B-Application
kernel	B-Operating_System
mainline	O
3.17	O
for	O
supporting	O
their	O
Graphics	O
Core	O
Next-based	O
Radeon	B-Device
graphics	B-Device
cards	I-Device
.	O
</s>
<s>
The	O
so-called	O
HSA	B-Architecture
kernel	B-Application
driver	I-Application
resides	O
in	O
the	O
directory	O
,	O
while	O
the	O
DRM	B-Application
graphics	O
device	B-Application
drivers	I-Application
reside	O
in	O
and	O
augment	O
the	O
already	O
existing	O
DRM	B-Application
drivers	O
for	O
Radeon	B-Device
cards	O
.	O
</s>
<s>
This	O
very	O
first	O
implementation	O
focuses	O
on	O
a	O
single	O
"	O
Kaveri	O
"	O
APU	O
and	O
works	O
alongside	O
the	O
existing	O
Radeon	B-Device
kernel	B-Operating_System
graphics	O
driver	B-Application
(	O
kgd	O
)	O
.	O
</s>
<s>
Hardware	O
schedulers	O
are	O
used	O
to	O
perform	O
scheduling	O
and	O
offload	O
the	O
assignment	O
of	O
compute	O
queues	O
to	O
the	O
ACEs	O
from	O
the	O
driver	B-Application
to	O
hardware	O
,	O
by	O
buffering	O
these	O
queues	O
until	O
there	O
is	O
at	O
least	O
one	O
empty	O
queue	O
in	O
at	O
least	O
one	O
ACE	O
.	O
</s>
<s>
Part	O
of	O
the	O
scheduling	O
work	O
performed	O
includes	O
prioritized	O
queues	O
which	O
allow	O
critical	O
tasks	O
to	O
run	O
at	O
a	O
higher	O
priority	O
than	O
other	O
tasks	O
without	O
requiring	O
the	O
lower	O
priority	O
tasks	O
to	O
be	O
preempted	O
to	O
run	O
the	O
high	O
priority	O
task	O
,	O
therefore	O
allowing	O
the	O
tasks	O
to	O
run	O
concurrently	O
with	O
the	O
high	O
priority	O
tasks	O
scheduled	O
to	O
hog	O
the	O
GPU	B-Architecture
as	O
much	O
as	O
possible	O
while	O
letting	O
other	O
tasks	O
use	O
the	O
resources	O
that	O
the	O
high	O
priority	O
tasks	O
are	O
not	O
using	O
.	O
</s>
<s>
They	O
were	O
first	O
introduced	O
in	O
the	O
fourth	O
generation	O
GCN	O
microarchitecture	B-General_Concept
,	O
but	O
were	O
present	O
in	O
the	O
third	O
generation	O
GCN	O
microarchitecture	B-General_Concept
for	O
internal	O
testing	O
purposes	O
.	O
</s>
<s>
A	O
driver	B-Application
update	O
has	O
enabled	O
the	O
hardware	O
schedulers	O
in	O
third	O
generation	O
GCN	O
parts	O
for	O
production	O
use	O
.	O
</s>
<s>
This	O
unit	O
was	O
introduced	O
with	O
the	O
fourth	O
generation	O
GCN	O
microarchitecture	B-General_Concept
.	O
</s>
<s>
The	O
GCN	O
1	O
microarchitecture	B-General_Concept
was	O
used	O
in	O
several	O
Radeon	B-Device
HD	I-Device
7000	O
series	O
graphics	B-Device
cards	I-Device
.	O
</s>
<s>
ZeroCore	O
Power	O
is	O
a	O
long	O
idle	O
power	O
saving	O
technology	O
,	O
shutting	O
off	O
functional	O
units	O
of	O
the	O
GPU	B-Architecture
when	O
not	O
in	O
use	O
.	O
</s>
<s>
Discrete	B-Device
GPUs	I-Device
(	O
Southern	O
Islands	O
family	O
)	O
:	O
</s>
<s>
The	O
2nd	O
generation	O
of	O
GCN	O
was	O
introduced	O
with	O
the	O
Radeon	B-Device
HD	I-Device
7790	O
and	O
is	O
also	O
found	O
in	O
the	O
Radeon	B-Device
HD	I-Device
8770	O
,	O
R7	O
260/260X	O
,	O
R9	O
290/290X	O
,	O
R9	B-Device
295X2	I-Device
,	O
R7	B-Device
360	I-Device
,	O
and	O
R9	O
390/390X	O
,	O
as	O
well	O
as	O
Steamroller-based	O
desktop	O
"	O
Kaveri	O
"	O
APUs	O
and	O
mobile	O
"	O
Kaveri	O
"	O
APUs	O
and	O
in	O
the	O
Puma-based	O
"	O
Beema	O
"	O
and	O
"	O
Mullins	O
"	O
APUs	O
.	O
</s>
<s>
A	O
Shader	O
Engine	O
comprises	O
one	O
geometry	O
processor	O
,	O
up	O
to	O
44	O
CUs	O
(	O
Hawaii	O
chip	O
)	O
,	O
rasterizers	O
,	O
ROPs	B-General_Concept
,	O
and	O
L1	O
cache	B-General_Concept
.	O
</s>
<s>
Not	O
part	O
of	O
a	O
Shader	O
Engine	O
is	O
the	O
Graphics	O
Command	O
Processor	O
,	O
the	O
8	O
ACEs	O
,	O
the	O
L2	O
cache	B-General_Concept
and	O
memory	O
controllers	O
as	O
well	O
as	O
the	O
audio	O
and	O
video	B-Architecture
accelerators	I-Architecture
,	O
the	O
display	O
controllers	O
,	O
the	O
2	O
DMA	B-General_Concept
controllers	I-General_Concept
and	O
the	O
PCIe	O
interface	O
.	O
</s>
<s>
At	O
AMD	O
Developer	O
Summit	O
(	O
APU	O
)	O
in	O
November	O
2013	O
Michael	O
Mantor	O
presented	O
the	O
Radeon	B-Device
R9	I-Device
290X	O
.	O
</s>
<s>
Discrete	B-Device
GPUs	I-Device
(	O
Sea	B-General_Concept
Islands	I-General_Concept
family	O
)	O
:	O
</s>
<s>
GCN	O
3rd	O
generation	O
was	O
introduced	O
in	O
2014	O
with	O
the	O
Radeon	B-Device
R9	I-Device
285	O
and	O
R9	O
M295X	O
,	O
which	O
have	O
the	O
"	O
Tonga	O
"	O
GPU	B-Architecture
.	O
</s>
<s>
It	O
features	O
improved	O
tessellation	B-Algorithm
performance	O
,	O
lossless	O
delta	O
color	O
compression	O
to	O
reduce	O
memory	O
bandwidth	O
usage	O
,	O
an	O
updated	O
and	O
more	O
efficient	O
instruction	B-General_Concept
set	I-General_Concept
,	O
a	O
new	O
high	O
quality	O
scaler	O
for	O
video	O
,	O
and	O
a	O
new	O
multimedia	O
engine	O
(	O
video	O
encoder/decoder	O
)	O
.	O
</s>
<s>
Delta	O
color	O
compression	O
is	O
supported	O
in	O
Mesa	B-Application
.	O
</s>
<s>
discrete	B-Device
GPUs	I-Device
:	O
</s>
<s>
GPUs	B-Architecture
of	O
the	O
Arctic	O
Islands-family	O
were	O
introduced	O
in	O
Q2	O
of	O
2016	O
with	O
the	O
AMD	B-Device
Radeon	I-Device
400	I-Device
series	I-Device
.	O
</s>
<s>
The	O
fourth	O
generation	O
GCN	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
is	O
compatible	O
with	O
the	O
third	O
generation	O
.	O
</s>
<s>
It	O
is	O
an	O
optimization	O
for	O
14nm	B-Algorithm
FinFET	O
process	O
enabling	O
higher	O
GPU	B-Architecture
clock	O
speeds	O
than	O
with	O
the	O
3rd	O
GCN	O
generation	O
.	O
</s>
<s>
Architectural	O
improvements	O
include	O
new	O
hardware	O
schedulers	O
,	O
a	O
new	O
primitive	O
discard	O
accelerator	O
,	O
a	O
new	O
display	O
controller	O
,	O
and	O
an	O
updated	O
UVD	O
that	O
can	O
decode	O
HEVC	B-Algorithm
at	O
4K	O
resolutions	O
at	O
60	O
frames	O
per	O
second	O
with	O
10	O
bits	O
per	O
color	O
channel	O
.	O
</s>
<s>
discrete	B-Device
GPUs	I-Device
:	O
</s>
<s>
In	O
addition	O
to	O
dedicated	O
GPUs	B-Architecture
,	O
Polaris	O
is	O
utilized	O
in	O
the	O
APUs	O
of	O
the	O
PlayStation	O
4	O
Pro	O
and	O
Xbox	O
One	O
X	O
,	O
titled	O
"	O
Neo	O
"	O
and	O
"	O
Scorpio	O
"	O
,	O
respectively	O
.	O
</s>
<s>
FP64	O
performance	O
of	O
all	O
GCN	O
4th	O
generation	O
GPUs	B-Architecture
is	O
1/16	O
of	O
FP32	O
performance	O
.	O
</s>
<s>
The	O
new	O
design	O
was	O
expected	O
to	O
increase	O
instructions	O
per	O
clock	O
,	O
higher	O
clock	O
speeds	O
,	O
support	O
for	O
HBM2	O
,	O
a	O
larger	O
memory	O
address	B-General_Concept
space	I-General_Concept
.	O
</s>
<s>
The	O
discrete	B-Device
graphics	I-Device
chipsets	O
also	O
include	O
"	O
HBCC	O
(	O
High	O
Bandwidth	O
Cache	B-General_Concept
Controller	O
)	O
"	O
,	O
but	O
not	O
when	O
integrated	O
into	O
APUs	O
.	O
</s>
<s>
Additionally	O
,	O
the	O
new	O
chips	O
were	O
expected	O
to	O
include	O
improvements	O
in	O
the	O
Rasterisation	O
and	O
Render	B-General_Concept
output	I-General_Concept
units	I-General_Concept
.	O
</s>
<s>
Nvidia	O
introduced	O
tile-based	O
rasterization	O
and	O
binning	O
with	O
Maxwell	B-General_Concept
,	O
and	O
this	O
was	O
a	O
big	O
reason	O
for	O
Maxwell	B-General_Concept
's	O
efficiency	O
increase	O
.	O
</s>
<s>
In	O
January	O
,	O
AnandTech	O
assumed	O
that	O
Vega	B-Device
would	O
finally	O
catch	O
up	O
with	O
Nvidia	O
regarding	O
energy	O
efficiency	O
optimizations	O
due	O
to	O
the	O
new	O
"	O
DSBR	O
(	O
Draw	O
Stream	O
Binning	O
Rasterizer	O
)	O
"	O
to	O
be	O
introduced	O
with	O
Vega	B-Device
.	O
</s>
<s>
Vega	B-Device
10	O
and	O
Vega	B-Device
12	O
use	O
the	O
14	O
nm	O
FinFET	O
process	O
,	O
developed	O
by	O
Samsung	O
Electronics	O
and	O
licensed	O
to	O
GlobalFoundries	O
.	O
</s>
<s>
Vega	B-Device
20	I-Device
uses	O
the	O
7	O
nm	O
FinFET	O
process	O
developed	O
by	O
TSMC	O
.	O
</s>
<s>
discrete	B-Device
GPUs	I-Device
:	O
</s>
<s>
Vega	B-Device
20	I-Device
(	O
7	O
nm	O
TSMC	O
FinFET	O
process	O
)	O
found	O
on	O
"	O
Radeon	B-Device
Instinct	O
MI50	O
"	O
and	O
"	O
Radeon	B-Device
Instinct	O
MI60	O
"	O
-branded	O
accelerator	O
cards	O
,	O
"	O
Radeon	B-Device
Pro	O
Vega	B-Device
II	O
"	O
,	O
and	O
"	O
Radeon	B-Device
VII	O
"	O
-branded	O
graphics	B-Device
cards	I-Device
.	O
</s>
<s>
Double-precision	O
floating-point	O
(	O
FP64	O
)	O
performance	O
of	O
all	O
GCN	O
5th	O
generation	O
GPUs	B-Architecture
,	O
except	O
for	O
Vega	B-Device
20	I-Device
,	O
is	O
1/16	O
of	O
FP32	O
performance	O
.	O
</s>
<s>
For	O
Vega	B-Device
20	I-Device
with	O
Radeon	B-Device
Instinct	O
this	O
is	O
1/2	O
of	O
FP32	O
performance	O
.	O
</s>
<s>
For	O
Vega	B-Device
20	I-Device
with	O
Radeon	B-Device
VII	O
this	O
is	O
1/4	O
of	O
FP32	O
performance	O
.	O
</s>
<s>
All	O
GCN	O
5th	O
generation	O
GPUs	B-Architecture
support	O
half-precision	O
floating-point	O
(	O
FP16	O
)	O
calculations	O
which	O
is	O
double	O
of	O
FP32	O
performance	O
.	O
</s>
<s>
Table	O
contains	O
only	O
discrete	B-Device
GPU	I-Device
chips	O
(	O
including	O
mobile	O
)	O
.	O
</s>
<s>
Microarchitecture	B-General_Concept
GCN	O
1	O
GCN	O
2	O
GCN	O
3	O
GCN	O
4	O
GCN	O
5	O
Chip	O
Tahiti	O
Pitcairn	O
Cape	O
Verde	O
Oland	O
Hainan	O
Bonaire	O
Hawaii	O
Topaz	O
Tonga	O
Fiji	O
Ellesmere	O
Baffin	O
Lexa	O
Vega	B-Device
10	O
Vega	B-Device
12	O
Vega	B-Device
20	O
Code	O
name1	O
?	O
</s>
